Re: [PATCH v2 9/9] Documentation: hisi-pmu: Add introduction to HiSilicon

[Yicong Yang <yangyicong@huawei.com>]

Hi Yushan,

the subject seems to be truncated? should it be like below?

Documentation: hisi-pmu: Add introduction to HiSilicon v3 PMU

other comments inline. sorry for the late reply..

On 2025/8/21 21:50, Yushan Wang wrote:
> Some of HiSilicon V3 PMU hardware is divided into parts to fulfill the
> job of monitoring specific parts of a device.  Add description on that
> as well as the newly added ext operand for L3C PMU.
> 
> Signed-off-by: Yushan Wang <wangyushan12@huawei.com>
> ---
>  Documentation/admin-guide/perf/hisi-pmu.rst | 38 +++++++++++++++++++--
>  1 file changed, 36 insertions(+), 2 deletions(-)
> 
> diff --git a/Documentation/admin-guide/perf/hisi-pmu.rst b/Documentation/admin-guide/perf/hisi-pmu.rst
> index a307bce2f5c5..4c7584fe3c1a 100644
> --- a/Documentation/admin-guide/perf/hisi-pmu.rst
> +++ b/Documentation/admin-guide/perf/hisi-pmu.rst
> @@ -12,8 +12,8 @@ The HiSilicon SoC encapsulates multiple CPU and IO dies. Each CPU cluster
>  called Super CPU cluster (SCCL) and is made up of 6 CCLs. Each SCCL has
>  two HHAs (0 - 1) and four DDRCs (0 - 3), respectively.
>  
> -HiSilicon SoC uncore PMU driver
> --------------------------------
> +HiSilicon SoC uncore PMU v1

these (and below) new sections will break the ordered list of the options. this should not be
necessary to mention the version, just add the newly added options in the current way and
mention the introduced version should be enough.

> +---------------------------
>  
>  Each device PMU has separate registers for event counting, control and
>  interrupt, and the PMU driver shall register perf PMU drivers like L3C,
> @@ -56,6 +56,9 @@ Example usage of perf::
>    $# perf stat -a -e hisi_sccl3_l3c0/rd_hit_cpipe/ sleep 5
>    $# perf stat -a -e hisi_sccl3_l3c0/config=0x02/ sleep 5
>  
> +HiSilicon SoC uncore PMU v2
> +----------------------------------
> +
>  For HiSilicon uncore PMU v2 whose identifier is 0x30, the topology is the same
>  as PMU v1, but some new functions are added to the hardware.
>  
> @@ -113,6 +116,37 @@ uring channel. It is 2 bits. Some important codes are as follows:
>  - 2'b00: default value, count the events which sent to the both uring and
>    uring_ext channel;
>  
> +HiSilicon SoC uncore PMU v3
> +----------------------------------
> +
> +For HiSilicon uncore PMU v3 whose identifier is 0x40, some uncore PMUs are
> +further divided into parts for finer granularity of tracing, each part has its
> +own dedicated PMU, and all such PMUs together cover the monitoring job of events
> +on particular uncore device. Such PMUs are described in sysfs with name format
> +slightly changed::
> +
> +/sys/bus/event_source/devices/hisi_sccl{X}_<l3c{Y}_{Z}/ddrc{Y}_{Z}/noc{Y}_{Z}>
> +
> +Z is the sub-id, indicating different PMUs for part of hardware device.
> +
> +Usage of most PMUs with different sub-ids are identical. Specially, L3C PMU
> +provides ``ext`` operand to allow exploration of even finer granual statistics
> +of L3C PMU, L3C PMU driver use that as hint of termination when delivering perf
> +command to hardware:
> +
> +- ext=0: Default, could be used with event names.
> +- ext=1 and ext=2: Must be used with event codes, event names are not supported.
> +
> +An example of perf command could be::
> +
> +  $# perf stat -a -e hisi_sccl0_l3c1_0/event=0x1,ext=1/ sleep 5
> +
> +or::
> +
> +  $# perf stat -a -e hisi_sccl0_l3c1_0/rd_spipe/ sleep 5
> +
> +As above, ``hisi_sccl0_l3c1_0`` locates PMU on CPU cluster 0, L3 cache 1 pipe0.

this isn't correct. sccl0 indicates the Super CPU CLuster 0 which is already
described in the document.

thanks.