From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 95B30C433EF for ; Mon, 4 Jul 2022 03:53:00 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231644AbiGDDw6 (ORCPT ); Sun, 3 Jul 2022 23:52:58 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:32906 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229461AbiGDDwz (ORCPT ); Sun, 3 Jul 2022 23:52:55 -0400 Received: from mailgw02.mediatek.com (unknown [210.61.82.184]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 3B94E26D9; Sun, 3 Jul 2022 20:52:50 -0700 (PDT) X-UUID: dee92e9303ed433c8dfffdd29b6e8ad2-20220704 X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.7,REQID:78e3c066-32ee-4c05-b792-54b58b0d3671,OB:20,L OB:10,IP:0,URL:0,TC:0,Content:0,EDM:0,RT:0,SF:45,FILE:0,RULE:Release_Ham,A CTION:release,TS:45 X-CID-INFO: VERSION:1.1.7,REQID:78e3c066-32ee-4c05-b792-54b58b0d3671,OB:20,LOB :10,IP:0,URL:0,TC:0,Content:0,EDM:0,RT:0,SF:45,FILE:0,RULE:Release_Ham,ACT ION:release,TS:45 X-CID-META: VersionHash:87442a2,CLOUDID:968f82d6-5d6d-4eaf-a635-828a3ee48b7c,C OID:37d60373517a,Recheck:0,SF:28|17|19|48,TC:nil,Content:0,EDM:-3,IP:nil,U RL:0,File:nil,QS:nil,BEC:nil,COL:0 X-UUID: dee92e9303ed433c8dfffdd29b6e8ad2-20220704 Received: from mtkcas10.mediatek.inc [(172.21.101.39)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 1049489092; Mon, 04 Jul 2022 11:52:42 +0800 Received: from mtkcas10.mediatek.inc (172.21.101.39) by mtkmbs10n2.mediatek.inc (172.21.101.183) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.2.792.3; Mon, 4 Jul 2022 11:52:40 +0800 Received: from mtksdccf07 (172.21.84.99) by mtkcas10.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Mon, 4 Jul 2022 11:52:40 +0800 Message-ID: Subject: Re: [PATCH v20 3/4] arm64: dts: mt8183: add Mediatek MDP3 nodes From: CK Hu To: Moudy Ho , Mauro Carvalho Chehab , Rob Herring , Matthias Brugger , Krzysztof Kozlowski , Hans Verkuil CC: Chun-Kuang Hu , Rob Landley , Laurent Pinchart , , , , , , Alexandre Courbot , , , , , Benjamin Gaignard , AngeloGioacchino Del Regno , daoyuan huang , Ping-Hsun Wu , , , , , , , , Date: Mon, 4 Jul 2022 11:52:40 +0800 In-Reply-To: <20220630091408.6438-4-moudy.ho@mediatek.com> References: <20220630091408.6438-1-moudy.ho@mediatek.com> <20220630091408.6438-4-moudy.ho@mediatek.com> Content-Type: text/plain; charset="UTF-8" X-Mailer: Evolution 3.28.5-0ubuntu0.18.04.2 MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi, Moudy: On Thu, 2022-06-30 at 17:14 +0800, Moudy Ho wrote: > Add device nodes for Media Data Path 3 (MDP3) modules. > > Signed-off-by: Moudy Ho > Reviewed-by: AngeloGioacchino Del Regno < > angelogioacchino.delregno@collabora.com> > --- > arch/arm64/boot/dts/mediatek/mt8183.dtsi | 79 > +++++++++++++++++++++++- > 1 file changed, 78 insertions(+), 1 deletion(-) > > diff --git a/arch/arm64/boot/dts/mediatek/mt8183.dtsi > b/arch/arm64/boot/dts/mediatek/mt8183.dtsi > index 9485c1efc87c..938f0c4b7525 100644 > --- a/arch/arm64/boot/dts/mediatek/mt8183.dtsi > +++ b/arch/arm64/boot/dts/mediatek/mt8183.dtsi > @@ -1691,6 +1691,50 @@ > mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX > 0 0x1000>; > }; > > + mdp3-rdma0@14001000 { > + compatible = "mediatek,mt8183-mdp3-rdma"; > + reg = <0 0x14001000 0 0x1000>; > + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX > 0x1000 0x1000>; > + power-domains = <&spm > MT8183_POWER_DOMAIN_DISP>; > + clocks = <&mmsys CLK_MM_MDP_RDMA0>, > + <&mmsys CLK_MM_MDP_RSZ1>; > + iommus = <&iommu M4U_PORT_MDP_RDMA0>; > + mboxes = <&gce 20 CMDQ_THR_PRIO_LOWEST 0>, > + <&gce 21 CMDQ_THR_PRIO_LOWEST 0>; > + }; > + > + mdp3-rsz0@14003000 { > + compatible = "mediatek,mt8183-mdp3-rsz"; > + reg = <0 0x14003000 0 0x1000>; > + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX > 0x3000 0x1000>; > + clocks = <&mmsys CLK_MM_MDP_RSZ0>; > + }; > + > + mdp3-rsz1@14004000 { > + compatible = "mediatek,mt8183-mdp3-rsz"; > + reg = <0 0x14004000 0 0x1000>; > + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX > 0x4000 0x1000>; > + clocks = <&mmsys CLK_MM_MDP_RSZ1>; > + }; > + > + mdp3-wrot0@14005000 { > + compatible = "mediatek,mt8183-mdp3-wrot"; > + reg = <0 0x14005000 0 0x1000>; > + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX > 0x5000 0x1000>; > + power-domains = <&spm > MT8183_POWER_DOMAIN_DISP>; > + clocks = <&mmsys CLK_MM_MDP_WROT0>; > + iommus = <&iommu M4U_PORT_MDP_WROT0>; > + }; > + > + mdp3-wdma@14006000 { > + compatible = "mediatek,mt8183-mdp3-wdma"; > + reg = <0 0x14006000 0 0x1000>; > + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX > 0x6000 0x1000>; > + power-domains = <&spm > MT8183_POWER_DOMAIN_DISP>; > + clocks = <&mmsys CLK_MM_MDP_WDMA0>; > + iommus = <&iommu M4U_PORT_MDP_WDMA0>; > + }; > + > ovl0: ovl@14008000 { > compatible = "mediatek,mt8183-disp-ovl"; > reg = <0 0x14008000 0 0x1000>; > @@ -1809,7 +1853,33 @@ > interrupts = ; > power-domains = <&spm > MT8183_POWER_DOMAIN_DISP>; > mediatek,gce-events = > , > - DONE1>; > + DONE1>, > + >, > + >, This event is sent from MDP_RDMA0 to GCE, so move this event to MDP_RDMA0 node. > + > , > + > , > + >, > + >, > + >, > + >, > + >, This event is sent from MDP_WDMA0 to GCE, so move this event to MDP_WDMA0 node. > + E_P2_0>, > + E_P2_1>, > + E_P2_2>, > + E_P2_3>, > + E_P2_4>, > + E_P2_5>, > + E_P2_6>, > + E_P2_7>, > + E_P2_8>, > + E_P2_9>, > + E_P2_10>, > + E_P2_11>, > + E_P2_12>, > + E_P2_13>, > + E_P2_14>, > + , This event is sent from WPE_A to GCE, so move this event to WPE_A node. Regards, CK > + ; > mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX > 0x6000 0x1000>; > }; > > @@ -1834,6 +1904,13 @@ > power-domains = <&spm > MT8183_POWER_DOMAIN_DISP>; > }; > > + mdp3-ccorr@1401c000 { > + compatible = "mediatek,mt8183-mdp3-ccorr"; > + reg = <0 0x1401c000 0 0x1000>; > + mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX > 0xc000 0x1000>; > + clocks = <&mmsys CLK_MM_MDP_CCORR>; > + }; > + > imgsys: syscon@15020000 { > compatible = "mediatek,mt8183-imgsys", > "syscon"; > reg = <0 0x15020000 0 0x1000>;