From: "Ng, Adrian Ho Yin" <adrian.ho.yin.ng@altera.com>
To: Dinh Nguyen <dinguyen@kernel.org>, Rob Herring <robh@kernel.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Conor Dooley <conor+dt@kernel.org>,
devicetree@vger.kernel.org, linux-kernel@vger.kernel.org
Subject: Re: [PATCH 2/2] firmware: stratix10-svc: add support for agilex5
Date: Thu, 23 Jul 2026 10:43:51 +0800 [thread overview]
Message-ID: <d77c0450-8d0c-4f05-9d92-5998c72821d9@altera.com> (raw)
In-Reply-To: <35520e5f-eccd-4516-875f-2a042107b237@kernel.org>
On 7/21/2026 7:59 AM, Dinh Nguyen wrote:
>
>
> On 6/22/26 08:44, Adrian Ng Ho Yin wrote:
>> On Agilex5 the DDR base address starts at 0x8000_0000, which is
>> outside the addressable range of the SDM. The SMMU is used to remap
>> DDR-allocated buffers to an IOVA within the SDM-accessible 0-512MB
>> window. Return -ENODEV at probe if no IOMMU domain is found for an
>> intel,agilex5-svc device.
>>
>> Configure a 29-bit DMA mask to constrain IOVA allocations to the
>> 0-512MB range accessible to the SDM. Agilex5 REV B introduced a
>> hardware SDM address remapper; bypass it via SMC so no additional
>> offset is applied to the IOVA, keeping the implementation
>> consistent across all Agilex5 revisions.
>>
>> ATF validates FPGA_CONFIG_WRITE addresses against the DDR range
>> starting at 0x8000_0000. Since IOVAs are below 0x2000_0000, the
>> driver adds 0x8000_0000 to the IOVA before the SMC call so ATF's
>> is_address_in_ddr_range() check passes. ATF then strips the offset
>> and uses the SMMU to translate the remaining IOVA to the underlying
>> physical memory for SDM access.
>>
>> The firmware COMPLETED_WRITE response returns the raw IOVA without
>> the 0x8000_0000 offset. Compensate by storing dma_addr_offset in
>> the controller and adding it back before the svc_pa_to_va() lookup.
>> dma_addr_offset is zero on non-SMMU paths so existing platforms are
>> unaffected.
>>
>> Fix a pre-existing bug in stratix10_svc_free_memory() where an
>> unknown-address fallthrough called list_del(&svc_data_mem),
>> corrupting the list head. Replace it with dev_warn().
>>
>> Register a devm cleanup action at probe to reclaim any DMA
>> coherent buffers that service clients fail to free before driver
>> unbind, preventing memory leaks across probe/remove cycles.
>>
>> Signed-off-by: Adrian Ng Ho Yin <adrian.ho.yin.ng@altera.com>
>
> There's alot going on with this patch! Can you split it up into smaller
> bits? And what part of this patch needed for the DTS patch?
Will split the commit into smaller commits and resend.
In the DTS patch i've removed the status="disabled" property in the smmu
node which is required to enable SMMU on Agilex5 by default and allow
the SVC driver to retrieve the attached IOMMU domain.
would you prefer if i send the DTS changes separately?
Thanks
Adrian>
> Dinh
prev parent reply other threads:[~2026-07-23 2:44 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-06-22 13:44 [PATCH 0/2] Add FPGA configuration and partial reconfiguration support for Agilex5 Adrian Ng Ho Yin
2026-06-22 13:44 ` [PATCH 1/2] arm64: dts: socfpga: agilex5: add FPGA manager and region nodes Adrian Ng Ho Yin
2026-06-22 13:44 ` [PATCH 2/2] firmware: stratix10-svc: add support for agilex5 Adrian Ng Ho Yin
2026-07-20 23:59 ` Dinh Nguyen
2026-07-23 2:43 ` Ng, Adrian Ho Yin [this message]
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