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[130.180.211.218]) by smtp.googlemail.com with ESMTPSA id ffacd0b85a97d-42ac679c5dcsm5661874f8f.44.2025.11.07.03.36.15 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 07 Nov 2025 03:36:16 -0800 (PST) Message-ID: Date: Fri, 7 Nov 2025 12:36:14 +0100 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v5 2/2] iio: adc: Add the NXP SAR ADC support for the s32g2/3 platforms To: Andy Shevchenko Cc: jic23@kernel.org, dlechner@baylibre.com, nuno.sa@analog.com, andy@kernel.org, robh@kernel.org, conor+dt@kernel.org, krzk+dt@kernel.org, linux-iio@vger.kernel.org, s32@nxp.com, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, chester62515@gmail.com, mbrugger@suse.com, ghennadi.procopciuc@oss.nxp.com References: <20251017164238.1908585-1-daniel.lezcano@linaro.org> <20251017164238.1908585-3-daniel.lezcano@linaro.org> <050f96d5-e60c-4b33-b6d2-24fb3925e378@linaro.org> Content-Language: en-US From: Daniel Lezcano In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit On 10/31/25 13:45, Andy Shevchenko wrote: > On Fri, Oct 31, 2025 at 12:32:03PM +0100, Daniel Lezcano wrote: >> On 10/30/25 10:28, Andy Shevchenko wrote: >>> On Thu, Oct 30, 2025 at 09:27:21AM +0100, Daniel Lezcano wrote: >>>> On 10/18/25 22:12, Andy Shevchenko wrote: >>>>> On Fri, Oct 17, 2025 at 06:42:38PM +0200, Daniel Lezcano wrote: > > [ ... ] > >>>>>> + dma_samples = (u32 *)dma_buf->buf; >>>>> >>>>> Is it aligned properly for this type of casting? >>>> >>>> TBH, I don't know the answer :/ >>>> >>>> How can I check that ? >>> >>> Is buf defined as a pointer to u32 / int or bigger? or is it just byte buffer? >>> If the latter, how does the address of it being formed? Does it come from a heap >>> (memory allocator)? If yes, we are fine, as this is usually the case for all >>> (k)malloc'ed memory. >> >> buf is a byte buffer allocated with dmam_alloc_coherent(..., GFP_KERNEL) > > We are fine :-) > > ... > >>>>>> + dmaengine_tx_status(info->dma_chan, info->cookie, &state); >>>>> >>>>> No return value check? >>>> >>>> The return value is not necessary here because the caller of the callback >>>> will check with dma_submit_error() in case of error which covers the >>>> DMA_ERROR case and the other cases are not useful because the residue is >>>> taken into account right after. >>> >>> In some cases it might return DMA_PAUSE (and actually this is the correct way >>> to get residue, one needs to pause the channel to read it, otherwise it will >>> give outdated / incorrect information). >> >> But if the residue is checked in the callback routine without checking >> DMA_PAUSED, the result is the same no ? > > DMA in some corner cases might have already be charged for the next transfer. > Do you have a synchronisation between DMA start and residue check? > > I.o.w. this may work for your case, but in general it's not guaranteed. The proper > read of residue is to: pause DMA --> read residue --> resume DMA. > I'll use the new callback function dma_async_tx_callback_result() which should prevent that and allows to remove the spinlock at the same time -- Linaro.org │ Open source software for ARM SoCs Follow Linaro: Facebook | Twitter | Blog