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Tue, 03 Dec 2024 15:03:55 +0000 (GMT) Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA02.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 4B3F3r8g025733 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 3 Dec 2024 15:03:53 GMT Received: from [10.217.216.47] (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Tue, 3 Dec 2024 07:03:49 -0800 Message-ID: Date: Tue, 3 Dec 2024 20:33:46 +0530 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 2/3] arm64: dts: qcom: sa8775p: Add CPU OPP tables to scale DDR/L3 To: Konrad Dybcio , Dmitry Baryshkov CC: Brian Masney , Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , , , , Ajit Pandey , "Imran Shaik" , Taniya Das , "Satya Priya Kakitapalli" , Shivnandan Kumar References: <20241017-sa8775p-cpufreq-l3-ddr-scaling-v1-0-074e0fb80b33@quicinc.com> <20241017-sa8775p-cpufreq-l3-ddr-scaling-v1-2-074e0fb80b33@quicinc.com> <9179759d-7af1-409f-8130-1136c9ae4ecd@quicinc.com> <5c3d91e3-e9d3-4e8d-bd4f-f7cbe765dddc@oss.qualcomm.com> Content-Language: en-US From: Jagadeesh Kona In-Reply-To: <5c3d91e3-e9d3-4e8d-bd4f-f7cbe765dddc@oss.qualcomm.com> Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: 7bit X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: A1pciyluYGEhyE04isEvtUXARHh2q3PN X-Proofpoint-GUID: A1pciyluYGEhyE04isEvtUXARHh2q3PN X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 adultscore=0 mlxlogscore=730 bulkscore=0 impostorscore=0 mlxscore=0 suspectscore=0 spamscore=0 priorityscore=1501 lowpriorityscore=0 phishscore=0 malwarescore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2411120000 definitions=main-2412030128 On 11/30/2024 8:02 PM, Konrad Dybcio wrote: > On 14.11.2024 11:48 PM, Dmitry Baryshkov wrote: >> On Mon, Nov 11, 2024 at 06:39:48PM +0530, Jagadeesh Kona wrote: >>> >>> >>> On 10/17/2024 9:12 PM, Brian Masney wrote: >>>> On Thu, Oct 17, 2024 at 02:58:31PM +0530, Jagadeesh Kona wrote: >>>>> + cpu0_opp_table: opp-table-cpu0 { >>>>> + compatible = "operating-points-v2"; >>>>> + opp-shared; >>>>> + >>>>> + cpu0_opp_1267mhz: opp-1267200000 { >>>>> + opp-hz = /bits/ 64 <1267200000>; >>>>> + opp-peak-kBps = <6220800 29491200>; >>>>> + }; >>>>> + >>>>> + cpu0_opp_1363mhz: opp-1363200000 { >>>>> + opp-hz = /bits/ 64 <1363200000>; >>>>> + opp-peak-kBps = <6220800 29491200>; >>>>> + }; >>>> >>>> [snip] >>>> >>>>> + cpu4_opp_table: opp-table-cpu4 { >>>>> + compatible = "operating-points-v2"; >>>>> + opp-shared; >>>>> + >>>>> + cpu4_opp_1267mhz: opp-1267200000 { >>>>> + opp-hz = /bits/ 64 <1267200000>; >>>>> + opp-peak-kBps = <6220800 29491200>; >>>>> + }; >>>>> + >>>>> + cpu4_opp_1363mhz: opp-1363200000 { >>>>> + opp-hz = /bits/ 64 <1363200000>; >>>>> + opp-peak-kBps = <6220800 29491200>; >>>>> + }; >>>> >>>> There's no functional differences in the cpu0 and cpu4 opp tables. Can >>>> a single table be used? >>>> >>>> This aligns with my recollection that this particular SoC only has the >>>> gold cores. >>>> >>>> Brian >>>> >>> >>> Thanks Brian for your review. Sorry for the delayed response. >>> >>> We require separate OPP tables for CPU0 and CPU4 to allow independent >>> scaling of DDR and L3 frequencies for each CPU domain, with the final >>> DDR and L3 frequencies being an aggregate of both. >>> >>> If we use a single OPP table for both CPU domains, then _allocate_opp_table() [1] >>> won't be invoked for CPU4. As a result both CPU devices will end up in sharing >>> the same ICC path handle, which could lead to one CPU device overwriting the bandwidth >>> votes of other. > > Oh that's a fun find.. clocks get the same treatment.. very bad, > but may explain some schroedingerbugs. > > Taking a peek at some code paths, wouldn't dropping opp-shared > solve our issues? dev_pm_opp_set_sharing_cpus() overrides it > > Konrad Thanks Konrad for your review. Yes, correct. I tried dropping opp-shared but it is again getting set due to dev_pm_opp_set_sharing_cpus(). Thanks, Jagadeesh