From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754372AbcIEHsp (ORCPT ); Mon, 5 Sep 2016 03:48:45 -0400 Received: from mx08-00178001.pphosted.com ([91.207.212.93]:38185 "EHLO mx07-00178001.pphosted.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1752246AbcIEHsn (ORCPT ); Mon, 5 Sep 2016 03:48:43 -0400 Subject: Re: [PATCH v3 2/9] drivers: irqchip: Add STM32 external interrupts support To: Thomas Gleixner References: <1472830398-13275-1-git-send-email-alexandre.torgue@st.com> <1472830398-13275-3-git-send-email-alexandre.torgue@st.com> CC: Maxime Coquelin , Jason Cooper , Marc Zyngier , Linus Walleij , Mark Rutland , Rob Herring , , , , , , Daniel Thompson , , From: Alexandre Torgue Message-ID: Date: Mon, 5 Sep 2016 09:47:27 +0200 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:45.0) Gecko/20100101 Thunderbird/45.2.0 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset="windows-1252"; format=flowed Content-Transfer-Encoding: 7bit X-Originating-IP: [10.48.0.2] X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10432:,, definitions=2016-09-05_04:,, signatures=0 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi Thomas, On 09/02/2016 08:57 PM, Thomas Gleixner wrote: > Alexandre, > > On Fri, 2 Sep 2016, Alexandre TORGUE wrote: > > This all looks very reasonable. The only complaint I have is your variable > declaration ordering or the lack thereof. > > 1) >> + struct irq_domain *domain = irq_desc_get_handler_data(desc); >> + struct irq_chip_generic *gc = domain->gc->gc[0]; >> + struct irq_chip *chip = irq_desc_get_chip(desc); >> + unsigned long pending; >> + int n; > > 2) >> + struct irq_chip_generic *gc = irq_data_get_irq_chip_data(data); >> + u32 rtsr, ftsr; >> + int pin = data->hwirq; > > 3) >> + struct irq_chip_generic *gc = irq_data_get_irq_chip_data(data); >> + int pin = data->hwirq; >> + u32 emr; > > 4) >> + irq_hw_number_t hwirq; >> + struct irq_fwspec *fwspec = data; >> + struct irq_chip_generic *gc = d->gc->gc[0]; > > 5) >> + int nr_irqs, nr_exti, ret, i; >> + unsigned int clr = IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN; >> + struct irq_domain *domain; >> + struct irq_chip_generic *gc; >> + void *base; > > #1 and 3 have the ordering which is preferred in the irq code. > > #2, #4 and #5 are three permutations which are way harder to read. > >> + struct irq_chip_generic *gc = irq_data_get_irq_chip_data(data); >> + int pin = data->hwirq; >> + u32 rtsr, ftsr; > >> + struct irq_chip_generic *gc = d->gc->gc[0]; >> + struct irq_fwspec *fwspec = data; >> + irq_hw_number_t hwirq; > >> + unsigned int clr = IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN; >> + int nr_irqs, nr_exti, ret, i; >> + struct irq_chip_generic *gc; >> + struct irq_domain *domain; >> + void *base; > > Can you spot the difference? Thanks for review and for proposal. It Will be in next version. Regards Alex > > Thanks, > > tglx >