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([2a01:e0a:3d9:2080:9086:bd36:16a7:1f8b]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3b79c489e81sm44885723f8f.68.2025.08.12.06.39.00 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 12 Aug 2025 06:39:00 -0700 (PDT) Message-ID: Date: Tue, 12 Aug 2025 15:39:00 +0200 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird From: neil.armstrong@linaro.org Reply-To: Neil Armstrong Subject: Re: [PATCH 2/2] phy: qcom-mipi-csi2: Add a CSI2 MIPI D-PHY driver To: Bryan O'Donoghue , Vinod Koul , Kishon Vijay Abraham I , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: Bryan O'Donoghue , Vladimir Zapolskiy , linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, linux-media@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org References: <20250710-x1e-csi2-phy-v1-0-74acbb5b162b@linaro.org> <20250710-x1e-csi2-phy-v1-2-74acbb5b162b@linaro.org> Content-Language: en-US, fr Autocrypt: addr=neil.armstrong@linaro.org; keydata= xsBNBE1ZBs8BCAD78xVLsXPwV/2qQx2FaO/7mhWL0Qodw8UcQJnkrWmgTFRobtTWxuRx8WWP GTjuhvbleoQ5Cxjr+v+1ARGCH46MxFP5DwauzPekwJUD5QKZlaw/bURTLmS2id5wWi3lqVH4 BVF2WzvGyyeV1o4RTCYDnZ9VLLylJ9bneEaIs/7cjCEbipGGFlfIML3sfqnIvMAxIMZrvcl9 qPV2k+KQ7q+aXavU5W+yLNn7QtXUB530Zlk/d2ETgzQ5FLYYnUDAaRl+8JUTjc0CNOTpCeik 80TZcE6f8M76Xa6yU8VcNko94Ck7iB4vj70q76P/J7kt98hklrr85/3NU3oti3nrIHmHABEB AAHNKk5laWwgQXJtc3Ryb25nIDxuZWlsLmFybXN0cm9uZ0BsaW5hcm8ub3JnPsLAkQQTAQoA OwIbIwULCQgHAwUVCgkICwUWAgMBAAIeAQIXgBYhBInsPQWERiF0UPIoSBaat7Gkz/iuBQJk Q5wSAhkBAAoJEBaat7Gkz/iuyhMIANiD94qDtUTJRfEW6GwXmtKWwl/mvqQtaTtZID2dos04 YqBbshiJbejgVJjy+HODcNUIKBB3PSLaln4ltdsV73SBcwUNdzebfKspAQunCM22Mn6FBIxQ GizsMLcP/0FX4en9NaKGfK6ZdKK6kN1GR9YffMJd2P08EO8mHowmSRe/ExAODhAs9W7XXExw UNCY4pVJyRPpEhv373vvff60bHxc1k/FF9WaPscMt7hlkbFLUs85kHtQAmr8pV5Hy9ezsSRa GzJmiVclkPc2BY592IGBXRDQ38urXeM4nfhhvqA50b/nAEXc6FzqgXqDkEIwR66/Gbp0t3+r yQzpKRyQif3OwE0ETVkGzwEIALyKDN/OGURaHBVzwjgYq+ZtifvekdrSNl8TIDH8g1xicBYp QTbPn6bbSZbdvfeQPNCcD4/EhXZuhQXMcoJsQQQnO4vwVULmPGgtGf8PVc7dxKOeta+qUh6+ SRh3vIcAUFHDT3f/Zdspz+e2E0hPV2hiSvICLk11qO6cyJE13zeNFoeY3ggrKY+IzbFomIZY 4yG6xI99NIPEVE9lNBXBKIlewIyVlkOaYvJWSV+p5gdJXOvScNN1epm5YHmf9aE2ZjnqZGoM Mtsyw18YoX9BqMFInxqYQQ3j/HpVgTSvmo5ea5qQDDUaCsaTf8UeDcwYOtgI8iL4oHcsGtUX oUk33HEAEQEAAcLAXwQYAQIACQUCTVkGzwIbDAAKCRAWmrexpM/4rrXiB/sGbkQ6itMrAIfn M7IbRuiSZS1unlySUVYu3SD6YBYnNi3G5EpbwfBNuT3H8//rVvtOFK4OD8cRYkxXRQmTvqa3 3eDIHu/zr1HMKErm+2SD6PO9umRef8V82o2oaCLvf4WeIssFjwB0b6a12opuRP7yo3E3gTCS KmbUuLv1CtxKQF+fUV1cVaTPMyT25Od+RC1K+iOR0F54oUJvJeq7fUzbn/KdlhA8XPGzwGRy 4zcsPWvwnXgfe5tk680fEKZVwOZKIEuJC3v+/yZpQzDvGYJvbyix0lHnrCzq43WefRHI5XTT QbM0WUIBIcGmq38+OgUsMYu4NzLu7uZFAcmp6h8g Organization: Linaro In-Reply-To: <20250710-x1e-csi2-phy-v1-2-74acbb5b162b@linaro.org> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit On 10/07/2025 18:16, Bryan O'Donoghue wrote: > Add a new MIPI CSI2 driver in D-PHY mode initially. The entire set of > existing CAMSS CSI PHY init sequences are imported in order to save time > and effort in later patches. > > In-line with other PHY drivers the process node name is omitted from the > compat string while the soc name is included. > > At the moment we follow the assignment of lane positions - the bitmap of > physical input lanes to logical lane numbers as a linear list per the > existing DPHY @lanes data-member. > > This is fine for us in upstream since we also map the lanes contiguously > but, our hardware can support different lane mappings so we should in the > future extend out the DPHY structure to capture the mapping. > > The Qualcomm 3PH class of PHYs can do both D-PHY and C-PHY mode. For now only > D-PHY is supported. > > In porting some of the logic over from camss-csiphy*.c to here its also > possible to rationalise some of the code. > > In particular use of regulator_bulk and clk_bulk as well as dropping the > seemingly useless and unused interrupt handler. > > The PHY sequences and a lot of the logic that goes with them are well proven > in CAMSS and mature so the main thing to watch out for here is how to get > the right sequencing of regulators, clocks and register-writes. > > Signed-off-by: Bryan O'Donoghue > --- > MAINTAINERS | 11 + > drivers/phy/qualcomm/Kconfig | 11 + > drivers/phy/qualcomm/Makefile | 6 + > drivers/phy/qualcomm/phy-qcom-mipi-csi2-3ph-dphy.c | 491 +++++++++++++++++++++ > drivers/phy/qualcomm/phy-qcom-mipi-csi2-core.c | 281 ++++++++++++ > drivers/phy/qualcomm/phy-qcom-mipi-csi2.h | 101 +++++ > 6 files changed, 901 insertions(+) > > > +const struct mipi_csi2phy_clk_freq zero = { 0 }; > + > +const struct mipi_csi2phy_clk_freq dphy_4nm_x1e_csiphy = { > + .freq = { > + 300000000, 400000000, 480000000 > + }, > + .num_freq = 3, > +}; > + > +const struct mipi_csi2phy_clk_freq dphy_4nm_x1e_csiphy_timer = { > + .freq = { > + 266666667, 400000000 > + }, > + .num_freq = 2, > +}; > + > +const struct mipi_csi2phy_soc_cfg mipi_csi2_dphy_4nm_x1e = { > + .ops = &phy_qcom_mipi_csi2_ops_3ph_1_0, > + .reg_info = { > + .init_seq = lane_regs_x1e80100, > + .lane_array_size = ARRAY_SIZE(lane_regs_x1e80100), > + .offset = 0x1000, > + .generation = GEN2, > + }, > + .supply_names = (const char *[]){ > + "vdda-0p8", > + "vdda-1p2" > + }, > + .num_supplies = 2, > + .clk_names = (const char *[]) { > + "camnoc_axi", > + "cpas_ahb", > + "csiphy", > + "csiphy_timer" > + }, > + .num_clk = 4, > + .clk_freq = { > + zero, It seems clang doesn't like this at all: drivers/phy/qualcomm/phy-qcom-mipi-csi2-3ph-dphy.c:486:3: error: initializer element is not a compile-time constant zero, ^~~~ 1 error generated. > + zero, > + dphy_4nm_x1e_csiphy, > + dphy_4nm_x1e_csiphy_timer, > + }, > +};