From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 61500183CCB; Thu, 8 Aug 2024 09:39:28 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1723109968; cv=none; b=EJP122RdF9DUdWpD/yIjo4LvRq3/PGAfay+qFeGltvJA3bwySIKX8k6tueznxxvqHyJlpQDWCHF/RC5gE8/lpL4VPu8nXqK9/iJ5sU0nhKFGtI7N1t14rsozZEo9EMAxlRg+L8yKx+NRFn7urRmN3b51pqr+s9+aiOx04eYi9iI= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1723109968; c=relaxed/simple; bh=S6uVSWM0fVB47Wnkpa/QXKdTn2ezvJoHADvHg7pwr8M=; h=Message-ID:Date:MIME-Version:Subject:To:Cc:References:From: In-Reply-To:Content-Type; b=S9p+Oo66p6+aO60kMXirmbmauXFQr/WE84AZRRNlXmiwrxHJas7ISe0XHK8iRgSlYtfNoeWPz9n9JaGtniz0KG8In6J/Fi/BZ8KbJmY8p1UaFWb/eKa+eCCZwkZDgJp7dD76Wm+MZdGmwkYLfNVOvFXfqJIPw91cTVXXGxwhO2o= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=n6c2bDlX; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="n6c2bDlX" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 334FFC32782; Thu, 8 Aug 2024 09:39:22 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1723109967; bh=S6uVSWM0fVB47Wnkpa/QXKdTn2ezvJoHADvHg7pwr8M=; h=Date:Subject:To:Cc:References:From:In-Reply-To:From; b=n6c2bDlXBPhXJqlwY+K4UPv6A+2oJ5MZfqt+SaFXmwdqruBUsysc/9yb6NPrj7Shv Jz+nsD5Zb5hIRC1QmwiqFOoQtX8e7OnR3iLwIXRdOoFIl1PPSX/fnMp38Znk+jJWX6 RQzsrJBhZcdo9L3rSj9MNDCFLM3e/NUNdHlXglhiZ32+eMWuXgIkf7GRukuLjGfUmp kQgQKVStrEaBGQrRdb6JmEsPtQ4px/jKAGDszyQMCeL1Ll5bysZdQLVzLQkboJnUHu UF41qevTtbQVNBG7ckGAPFQOeogqoHnfxq6kf1JZOljRTnPBShk03IK799A4CS/r/3 Utcf+lddang5w== Message-ID: Date: Thu, 8 Aug 2024 11:39:19 +0200 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2 6/7] clk: samsung: clk-pll: Add support for pll_1418x To: David Virag , Sylwester Nawrocki , Chanwoo Choi , Alim Akhtar , Michael Turquette , Stephen Boyd , Rob Herring , Conor Dooley Cc: linux-samsung-soc@vger.kernel.org, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org References: <20240806121157.479212-1-virag.david003@gmail.com> <20240806121157.479212-7-virag.david003@gmail.com> From: Krzysztof Kozlowski Content-Language: en-US Autocrypt: addr=krzk@kernel.org; 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charset=UTF-8 Content-Transfer-Encoding: 7bit On 06/08/2024 14:11, David Virag wrote: > pll1418x is used in Exynos7885 SoC for USB PHY clock. > Operation-wise it is very similar to pll0822x, except that MDIV is only > 9 bits wide instead of 10, and we use the CON1 register in the PLL > macro's "con" parameter instead of CON3 like this: > > PLL(pll_1418x, CLK_FOUT_USB_PLL, "fout_usb_pll", "oscclk", > PLL_LOCKTIME_PLL_USB, PLL_CON0_PLL_USB, > pll_usb_rate_table), > > Technically the PLL should work fine with pll0822x code if the PLL > tables are correct, but it's more "correct" to actually update the mask. > > Signed-off-by: David Virag > --- > drivers/clk/samsung/clk-pll.c | 20 ++++++++++++++++---- > drivers/clk/samsung/clk-pll.h | 1 + > 2 files changed, 17 insertions(+), 4 deletions(-) > > diff --git a/drivers/clk/samsung/clk-pll.c b/drivers/clk/samsung/clk-pll.c > index 4be879ab917e..c61a2810737c 100644 > --- a/drivers/clk/samsung/clk-pll.c > +++ b/drivers/clk/samsung/clk-pll.c > @@ -430,6 +430,9 @@ static const struct clk_ops samsung_pll36xx_clk_min_ops = { > #define PLL0822X_LOCK_STAT_SHIFT (29) > #define PLL0822X_ENABLE_SHIFT (31) > > +/* PLL1418x is similar to PLL0822x, except that MDIV is one bit smaller */ > +#define PLL1418X_MDIV_MASK (0x1FF) > + > static unsigned long samsung_pll0822x_recalc_rate(struct clk_hw *hw, > unsigned long parent_rate) > { > @@ -438,7 +441,10 @@ static unsigned long samsung_pll0822x_recalc_rate(struct clk_hw *hw, > u64 fvco = parent_rate; > > pll_con3 = readl_relaxed(pll->con_reg); > - mdiv = (pll_con3 >> PLL0822X_MDIV_SHIFT) & PLL0822X_MDIV_MASK; > + if (pll->type != pll_1418x) > + mdiv = (pll_con3 >> PLL0822X_MDIV_SHIFT) & PLL0822X_MDIV_MASK; > + else > + mdiv = (pll_con3 >> PLL0822X_MDIV_SHIFT) & PLL1418X_MDIV_MASK; > pdiv = (pll_con3 >> PLL0822X_PDIV_SHIFT) & PLL0822X_PDIV_MASK; > sdiv = (pll_con3 >> PLL0822X_SDIV_SHIFT) & PLL0822X_SDIV_MASK; > > @@ -468,9 +474,14 @@ static int samsung_pll0822x_set_rate(struct clk_hw *hw, unsigned long drate, > > /* Change PLL PMS values */ > pll_con3 = readl_relaxed(pll->con_reg); > - pll_con3 &= ~((PLL0822X_MDIV_MASK << PLL0822X_MDIV_SHIFT) | > - (PLL0822X_PDIV_MASK << PLL0822X_PDIV_SHIFT) | > - (PLL0822X_SDIV_MASK << PLL0822X_SDIV_SHIFT)); > + if (pll->type != pll_1418x) > + pll_con3 &= ~((PLL0822X_MDIV_MASK << PLL0822X_MDIV_SHIFT) | > + (PLL0822X_PDIV_MASK << PLL0822X_PDIV_SHIFT) | > + (PLL0822X_SDIV_MASK << PLL0822X_SDIV_SHIFT)); I think this part could be simpler. If I read it correctly, only mdiv mask is different, so create local variable mdiv_mask and set it in if-else block accordingly to the type. Then here you have non-conditional code: pll_con3 &= ~((mdiv_mask << PLL0822X_MDIV_SHIFT) | Best regards, Krzysztof