From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from vps0.lunn.ch (vps0.lunn.ch [156.67.10.101]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 433F81D514B; Wed, 19 Mar 2025 22:40:06 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=156.67.10.101 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1742424008; cv=none; b=mBi6PVyh5wCWDdBmSq3AUWSE2ZNG3llnzqLwYNIm50o4FAubOoTO9WvFC9/ttvByIY+6IpOWyNlWAgMvv5wtEyRuC7MlQk8B3ZfP/jbDFYSboMMdY3l15JLaJtqsk6zkXsSWvl4G0TMHPv4isbeXUz5Renwc//OKRRugd2CoCdg= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1742424008; c=relaxed/simple; bh=2uXPjstuKd5ETSY4ZLOwCzlCbA+Q99mIAJvMpF7vxsU=; h=Date:From:To:Cc:Subject:Message-ID:References:MIME-Version: Content-Type:Content-Disposition:In-Reply-To; b=acO0qHOyGYd5Dz5vvToeiRovJl7/KJEjXSiVRYHNYVu2csrl1RA5OL/Phkb40ZI+TRkbK6hwSqIlvlK9ikBnny+FxNliVtA/t80KZs0y4altnljE0E01pgV8bIyTJc4htQSi2/xe44DMB8Mm0NxwrLs9vzLupojvso7nwsjXEYY= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=lunn.ch; spf=pass smtp.mailfrom=lunn.ch; dkim=pass (1024-bit key) header.d=lunn.ch header.i=@lunn.ch header.b=awaNfGbp; arc=none smtp.client-ip=156.67.10.101 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=lunn.ch Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=lunn.ch Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=lunn.ch header.i=@lunn.ch header.b="awaNfGbp" DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lunn.ch; s=20171124; h=In-Reply-To:Content-Disposition:Content-Type:MIME-Version: References:Message-ID:Subject:Cc:To:From:Date:From:Sender:Reply-To:Subject: Date:Message-ID:To:Cc:MIME-Version:Content-Type:Content-Transfer-Encoding: Content-ID:Content-Description:Content-Disposition:In-Reply-To:References; bh=jTG3WnDFAfRFQDs0cUx1kwKiOP6BmpOLg7RMMJcqr7s=; b=awaNfGbpagVPUyFCmBEgPJBmul e9tPJGuvyQX/cvhie0Gzen6w0UIqucPHwRQq7lqNasTTazFhe+DK60szAbKolzU3XYaHFyzt0or44 01eTmdmeu014tYZJcfTanw14k5yoqvo9Fh+IUWcXPUAuQyz34EHR/nWevIkioAIety70=; Received: from andrew by vps0.lunn.ch with local (Exim 4.94.2) (envelope-from ) id 1tv24e-006Q5Z-KP; Wed, 19 Mar 2025 23:39:44 +0100 Date: Wed, 19 Mar 2025 23:39:44 +0100 From: Andrew Lunn To: Jonas Karlman Cc: Heiko Stuebner , Andrew Lunn , "David S . Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Maxime Coquelin , Alexandre Torgue , Philipp Zabel , Rob Herring , Krzysztof Kozlowski , Conor Dooley , David Wu , Yao Zi , netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-rockchip@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com Subject: Re: [PATCH net-next v3 3/5] net: stmmac: dwmac-rk: Move integrated_phy_powerup/down functions Message-ID: References: <20250319214415.3086027-1-jonas@kwiboo.se> <20250319214415.3086027-4-jonas@kwiboo.se> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20250319214415.3086027-4-jonas@kwiboo.se> On Wed, Mar 19, 2025 at 09:44:07PM +0000, Jonas Karlman wrote: > Rockchip RK3528 (and RV1106) has a different integrated PHY compared to > the integrated PHY on RK3228/RK3328. Current powerup/down operation is > not compatible with the integrated PHY found in these SoCs. > > Move the rk_gmac_integrated_phy_powerup/down functions to top of the > file to prepare for them to be called directly by a GMAC variant > specific powerup/down operation. > > Signed-off-by: Jonas Karlman Reviewed-by: Andrew Lunn > +#define RK_GRF_CON2_MACPHY_ID HIWORD_UPDATE(0x1234, 0xffff, 0) > +#define RK_GRF_CON3_MACPHY_ID HIWORD_UPDATE(0x35, 0x3f, 0) > + > +static void rk_gmac_integrated_phy_powerup(struct rk_priv_data *priv) > +{ > + if (priv->ops->integrated_phy_powerup) > + priv->ops->integrated_phy_powerup(priv); > + > + regmap_write(priv->grf, RK_GRF_MACPHY_CON0, RK_MACPHY_CFG_CLK_50M); > + regmap_write(priv->grf, RK_GRF_MACPHY_CON0, RK_GMAC2PHY_RMII_MODE); > + > + regmap_write(priv->grf, RK_GRF_MACPHY_CON2, RK_GRF_CON2_MACPHY_ID); > + regmap_write(priv->grf, RK_GRF_MACPHY_CON3, RK_GRF_CON3_MACPHY_ID); I know you are just moving code around.... Do you know what these MACPHY_ID are? I hope it is not what you get when you read PHY registers 2 and 3? Andrew