Re: [PATCH v6 4/8] x86/resctrl: Implement "io_alloc" enable/disable handlers

["Moger, Babu" <babu.moger@amd.com>]

Hi Reinette,

On 6/17/25 22:51, Reinette Chatre wrote:
> Hi Babu,
> 
> On 6/11/25 2:23 PM, Babu Moger wrote:
>> "io_alloc" enables direct insertion of data from I/O devices into the L3
>> cache.
> 
> Above is from resctrl perspective and resctrl does not limit this to L3. Here also
> I think L3 should be dropped.

Sure.

> 
>>
>> On AMD, "io_alloc" feature is backed by L3 Smart Data Cache Injection
>> Allocation Enforcement (SDCIAE). Change SDCIAE state by setting (to enable)
>> or clearing (to disable) bit 1 of MSR L3_QOS_EXT_CFG on all logical
>> processors within the cache domain.
>>
>> Introduce architecture-specific handlers to enable and disable the feature.
>>
>> The SDCIAE feature details are available in APM listed below [1].
>> [1] AMD64 Architecture Programmer's Manual Volume 2: System Programming
>> Publication # 24593 Revision 3.41 section 19.4.7 L3 Smart Data Cache
>> Injection Allocation Enforcement (SDCIAE)
>>
>> Link: https://bugzilla.kernel.org/show_bug.cgi?id=206537
>> Signed-off-by: Babu Moger <babu.moger@amd.com>
>> ---
> 
> ...
> 
>> ---
>>  arch/x86/include/asm/msr-index.h       |  1 +
>>  arch/x86/kernel/cpu/resctrl/internal.h |  5 ++++
>>  arch/x86/kernel/cpu/resctrl/rdtgroup.c | 40 ++++++++++++++++++++++++++
>>  include/linux/resctrl.h                | 21 ++++++++++++++
> 
> This hints the subject prefix should be "x86,fs/resctrl".

Sure.

> 
>>  4 files changed, 67 insertions(+)
>>
>> diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h
>> index b7dded3c8113..b92b04fa9888 100644
>> --- a/arch/x86/include/asm/msr-index.h
>> +++ b/arch/x86/include/asm/msr-index.h
>> @@ -1215,6 +1215,7 @@
>>  /* - AMD: */
>>  #define MSR_IA32_MBA_BW_BASE		0xc0000200
>>  #define MSR_IA32_SMBA_BW_BASE		0xc0000280
>> +#define MSR_IA32_L3_QOS_EXT_CFG		0xc00003ff
>>  #define MSR_IA32_EVT_CFG_BASE		0xc0000400
>>  
>>  /* AMD-V MSRs */
>> diff --git a/arch/x86/kernel/cpu/resctrl/internal.h b/arch/x86/kernel/cpu/resctrl/internal.h
>> index 5e3c41b36437..cfa519ea2875 100644
>> --- a/arch/x86/kernel/cpu/resctrl/internal.h
>> +++ b/arch/x86/kernel/cpu/resctrl/internal.h
>> @@ -37,6 +37,9 @@ struct arch_mbm_state {
>>  	u64	prev_msr;
>>  };
>>  
>> +/* Setting bit 1 in L3_QOS_EXT_CFG enables the SDCIAE feature. */
>> +#define SDCIAE_ENABLE_BIT		1
>> +
>>  /**
>>   * struct rdt_hw_ctrl_domain - Arch private attributes of a set of CPUs that share
>>   *			       a resource for a control function
>> @@ -102,6 +105,7 @@ struct msr_param {
>>   * @mon_scale:		cqm counter * mon_scale = occupancy in bytes
>>   * @mbm_width:		Monitor width, to detect and correct for overflow.
>>   * @cdp_enabled:	CDP state of this resource
>> + * @sdciae_enabled:	SDCIAE feature is enabled
> 
> nit: "SDCIAE feature (backing "io_alloc") is enabled"

Sure.

> 
>>   *
>>   * Members of this structure are either private to the architecture
>>   * e.g. mbm_width, or accessed via helpers that provide abstraction. e.g.
>> @@ -115,6 +119,7 @@ struct rdt_hw_resource {
>>  	unsigned int		mon_scale;
>>  	unsigned int		mbm_width;
>>  	bool			cdp_enabled;
>> +	bool			sdciae_enabled;
>>  };
>>  
>>  static inline struct rdt_hw_resource *resctrl_to_arch_res(struct rdt_resource *r)
>> diff --git a/arch/x86/kernel/cpu/resctrl/rdtgroup.c b/arch/x86/kernel/cpu/resctrl/rdtgroup.c
>> index 885026468440..3bdcd53b3ce3 100644
>> --- a/arch/x86/kernel/cpu/resctrl/rdtgroup.c
>> +++ b/arch/x86/kernel/cpu/resctrl/rdtgroup.c
>> @@ -229,6 +229,46 @@ bool resctrl_arch_get_cdp_enabled(enum resctrl_res_level l)
>>  	return rdt_resources_all[l].cdp_enabled;
>>  }
>>  
>> +inline bool resctrl_arch_get_io_alloc_enabled(struct rdt_resource *r)
> 
> As indicated by lkp the inline usage needs to be fixed.

I am assuming that you are referring to
https://www.kernel.org/doc/html/next/process/coding-style.html#the-inline-disease

I will remove inline attribute.


> 
>> +{
>> +	return resctrl_to_arch_res(r)->sdciae_enabled;
>> +}
>> +
>> +static void resctrl_sdciae_set_one_amd(void *arg)
>> +{
>> +	bool *enable = arg;
>> +
>> +	if (*enable)
>> +		msr_set_bit(MSR_IA32_L3_QOS_EXT_CFG, SDCIAE_ENABLE_BIT);
>> +	else
>> +		msr_clear_bit(MSR_IA32_L3_QOS_EXT_CFG, SDCIAE_ENABLE_BIT);
>> +}
>> +
>> +static void _resctrl_sdciae_enable(struct rdt_resource *r, bool enable)
>> +{
>> +	struct rdt_ctrl_domain *d;
>> +
>> +	/* Walking r->ctrl_domains, ensure it can't race with cpuhp */
>> +	lockdep_assert_cpus_held();
>> +
>> +	/* Update L3_QOS_EXT_CFG MSR on all the CPUs in all domains */
>> +	list_for_each_entry(d, &r->ctrl_domains, hdr.list)
>> +		on_each_cpu_mask(&d->hdr.cpu_mask, resctrl_sdciae_set_one_amd, &enable, 1);
>> +}
>> +
>> +int resctrl_arch_io_alloc_enable(struct rdt_resource *r, bool enable)
>> +{
>> +	struct rdt_hw_resource *hw_res = resctrl_to_arch_res(r);
>> +
>> +	if (hw_res->r_resctrl.cache.io_alloc_capable &&
>> +	    hw_res->sdciae_enabled != enable) {
>> +		_resctrl_sdciae_enable(r, enable);
>> +		hw_res->sdciae_enabled = enable;
>> +	}
>> +
>> +	return 0;
>> +}
>> +
>>  void resctrl_arch_reset_all_ctrls(struct rdt_resource *r)
>>  {
>>  	struct rdt_hw_resource *hw_res = resctrl_to_arch_res(r);
>> diff --git a/include/linux/resctrl.h b/include/linux/resctrl.h
>> index 0e8641e41100..06e8a1821702 100644
>> --- a/include/linux/resctrl.h
>> +++ b/include/linux/resctrl.h
>> @@ -531,6 +531,27 @@ void resctrl_arch_reset_rmid_all(struct rdt_resource *r, struct rdt_mon_domain *
>>   */
>>  void resctrl_arch_reset_all_ctrls(struct rdt_resource *r);
>>  
>> +/**
>> + * resctrl_arch_io_alloc_enable() - Enable/disable io_alloc feature.
>> + * @r:		The resctrl resource.
>> + * @enable:	Enable (true) or disable (false) io_alloc on resource @r.
>> + *
>> + * This can be called from any CPU.
>> + *
>> + * Return:
>> + * 0 on success, or non-zero on error.
> 
> Please change to "0 on success, <0 on error" to make clear it needs to be
> non-zero *and* negative to be considered error by resctrl fs.

Sure.

> 
>> + */
>> +int resctrl_arch_io_alloc_enable(struct rdt_resource *r, bool enable);
>> +
>> +/**
>> + * resctrl_arch_get_io_alloc_enabled() - Get io_alloc feature state.
>> + * @r:		The resctrl resource.
>> + *
>> + * Return:
>> + * true if io_alloc is enabled or false if disabled.
>> + */
>> +inline bool resctrl_arch_get_io_alloc_enabled(struct rdt_resource *r);
>> +
>>  extern unsigned int resctrl_rmid_realloc_threshold;
>>  extern unsigned int resctrl_rmid_realloc_limit;
>>  
> 
> Reinette
> 

-- 
Thanks
Babu Moger