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Thu, 20 Mar 2025 16:30:02 +0000 (GMT) Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA04.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 52KGU1Hn002162 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 20 Mar 2025 16:30:01 GMT Received: from [10.216.52.115] (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Thu, 20 Mar 2025 09:29:56 -0700 Message-ID: Date: Thu, 20 Mar 2025 21:59:53 +0530 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2 2/8] clk: qcom: common: Add support to configure PLL To: Bjorn Andersson CC: Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Konrad Dybcio , Ajit Pandey , Imran Shaik , Taniya Das , "Satya Priya Kakitapalli" , , , , References: <20250306-videocc-pll-multi-pd-voting-v2-0-0cd00612bc0e@quicinc.com> <20250306-videocc-pll-multi-pd-voting-v2-2-0cd00612bc0e@quicinc.com> Content-Language: en-US From: Jagadeesh Kona In-Reply-To: Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: 7bit X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: It6BhY4bK3QXtizPlqt_O2lb7eLEnuTv X-Authority-Analysis: v=2.4 cv=MJ5gmNZl c=1 sm=1 tr=0 ts=67dc428a cx=c_pps a=ouPCqIW2jiPt+lZRy3xVPw==:117 a=ouPCqIW2jiPt+lZRy3xVPw==:17 a=GEpy-HfZoHoA:10 a=IkcTkHD0fZMA:10 a=Vs1iUdzkB0EA:10 a=VwQbUJbxAAAA:8 a=COk6AnOGAAAA:8 a=a-Ujm2vb0zWFPRAAoKoA:9 a=QEXdDO2ut3YA:10 a=-_B0kFfA75AA:10 a=TjNXssC_j7lpFel5tvFf:22 X-Proofpoint-ORIG-GUID: It6BhY4bK3QXtizPlqt_O2lb7eLEnuTv X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1093,Hydra:6.0.680,FMLib:17.12.68.34 definitions=2025-03-20_04,2025-03-20_01,2024-11-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxlogscore=999 clxscore=1015 spamscore=0 priorityscore=1501 mlxscore=0 adultscore=0 phishscore=0 lowpriorityscore=0 malwarescore=0 impostorscore=0 bulkscore=0 suspectscore=0 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2502280000 definitions=main-2503200104 On 3/14/2025 4:09 AM, Bjorn Andersson wrote: > On Thu, Mar 06, 2025 at 02:25:34PM +0530, Jagadeesh Kona wrote: >> From: Taniya Das >> >> Integrate PLL configuration into clk_alpha_pll structure and add support >> for qcom_cc_clk_alpha_pll_configure() function which can be used to >> configure the clock controller PLLs from common core code. > > https://docs.kernel.org/process/submitting-patches.html#describe-your-changes > starts with "Describe your problem." > > I don't see a problem description here. > Yes, I will update the commit text with problem description in next series. >> >> Signed-off-by: Taniya Das >> Signed-off-by: Jagadeesh Kona >> --- >> drivers/clk/qcom/clk-alpha-pll.h | 2 ++ >> drivers/clk/qcom/common.c | 55 ++++++++++++++++++++++++++++++++++++++++ >> drivers/clk/qcom/common.h | 1 + >> 3 files changed, 58 insertions(+) >> >> diff --git a/drivers/clk/qcom/clk-alpha-pll.h b/drivers/clk/qcom/clk-alpha-pll.h >> index 79aca8525262211ae5295245427d4540abf1e09a..943320cdcd10a6c07fcd74dccb88be847dc086c2 100644 >> --- a/drivers/clk/qcom/clk-alpha-pll.h >> +++ b/drivers/clk/qcom/clk-alpha-pll.h >> @@ -81,6 +81,7 @@ struct pll_vco { >> * struct clk_alpha_pll - phase locked loop (PLL) >> * @offset: base address of registers >> * @regs: alpha pll register map (see @clk_alpha_pll_regs) >> + * @config: array of pll settings >> * @vco_table: array of VCO settings >> * @num_vco: number of VCO settings in @vco_table >> * @flags: bitmask to indicate features supported by the hardware >> @@ -90,6 +91,7 @@ struct clk_alpha_pll { >> u32 offset; >> const u8 *regs; >> >> + const struct alpha_pll_config *config; >> const struct pll_vco *vco_table; >> size_t num_vco; >> #define SUPPORTS_OFFLINE_REQ BIT(0) >> diff --git a/drivers/clk/qcom/common.c b/drivers/clk/qcom/common.c >> index 9e3380fd718198c9fe63d7361615a91c3ecb3d60..74d062b5da0647f7f2bd8fd7a004ffdb1116c1ea 100644 >> --- a/drivers/clk/qcom/common.c >> +++ b/drivers/clk/qcom/common.c >> @@ -13,6 +13,7 @@ >> #include >> >> #include "common.h" >> +#include "clk-alpha-pll.h" >> #include "clk-rcg.h" >> #include "clk-regmap.h" >> #include "reset.h" >> @@ -284,6 +285,60 @@ static int qcom_cc_icc_register(struct device *dev, >> desc->num_icc_hws, icd); >> } >> >> +static void qcom_cc_clk_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap) >> +{ >> + if (!pll->config || !pll->regs) >> + return; >> + >> + switch (GET_PLL_TYPE(pll)) { >> + case CLK_ALPHA_PLL_TYPE_LUCID_OLE: >> + clk_lucid_ole_pll_configure(pll, regmap, pll->config); >> + break; >> + case CLK_ALPHA_PLL_TYPE_LUCID_EVO: >> + clk_lucid_evo_pll_configure(pll, regmap, pll->config); >> + break; >> + case CLK_ALPHA_PLL_TYPE_TAYCAN_ELU: >> + clk_taycan_elu_pll_configure(pll, regmap, pll->config); >> + break; >> + case CLK_ALPHA_PLL_TYPE_RIVIAN_EVO: >> + clk_rivian_evo_pll_configure(pll, regmap, pll->config); >> + break; >> + case CLK_ALPHA_PLL_TYPE_TRION: >> + clk_trion_pll_configure(pll, regmap, pll->config); >> + break; >> + case CLK_ALPHA_PLL_TYPE_HUAYRA_2290: >> + clk_huayra_2290_pll_configure(pll, regmap, pll->config); >> + break; >> + case CLK_ALPHA_PLL_TYPE_FABIA: >> + clk_fabia_pll_configure(pll, regmap, pll->config); >> + break; >> + case CLK_ALPHA_PLL_TYPE_AGERA: >> + clk_agera_pll_configure(pll, regmap, pll->config); >> + break; >> + case CLK_ALPHA_PLL_TYPE_PONGO_ELU: >> + clk_pongo_elu_pll_configure(pll, regmap, pll->config); >> + break; >> + case CLK_ALPHA_PLL_TYPE_ZONDA: >> + case CLK_ALPHA_PLL_TYPE_ZONDA_OLE: >> + clk_zonda_pll_configure(pll, regmap, pll->config); >> + break; >> + case CLK_ALPHA_PLL_TYPE_STROMER: >> + case CLK_ALPHA_PLL_TYPE_STROMER_PLUS: >> + clk_stromer_pll_configure(pll, regmap, pll->config); >> + break; >> + case CLK_ALPHA_PLL_TYPE_DEFAULT: >> + case CLK_ALPHA_PLL_TYPE_DEFAULT_EVO: >> + case CLK_ALPHA_PLL_TYPE_HUAYRA: >> + case CLK_ALPHA_PLL_TYPE_HUAYRA_APSS: >> + case CLK_ALPHA_PLL_TYPE_BRAMMO: >> + case CLK_ALPHA_PLL_TYPE_BRAMMO_EVO: >> + clk_alpha_pll_configure(pll, regmap, pll->config); >> + break; >> + default: > > This would be annoying to hit when adding a new PLL type, a BUG(); would > be useful here. > Yes, will add BUG() here in next series. >> + break; >> + } >> +} >> + >> int qcom_cc_really_probe(struct device *dev, >> const struct qcom_cc_desc *desc, struct regmap *regmap) >> { >> diff --git a/drivers/clk/qcom/common.h b/drivers/clk/qcom/common.h >> index 7ace5d7f5836aa81431153ba92d8f14f2ffe8147..2066c8937936235d7bd03ab3225d4b3f4fb08dd0 100644 >> --- a/drivers/clk/qcom/common.h >> +++ b/drivers/clk/qcom/common.h >> @@ -18,6 +18,7 @@ struct clk_hw; >> #define PLL_BIAS_COUNT_MASK 0x3f >> #define PLL_VOTE_FSM_ENA BIT(20) >> #define PLL_VOTE_FSM_RESET BIT(21) >> +#define GET_PLL_TYPE(pll) ((pll->regs - clk_alpha_pll_regs[0]) / PLL_OFF_MAX_REGS) > > Why would this go in qcom/common.h, when clk_alpha_pll_regs is defined > in clk-alpha-pll.h? > Will move the macro to clk alpha pll code in next series. Thanks, Jagadeesh > Regards, > Bjorn > >> >> struct qcom_icc_hws_data { >> int master_id; >> >> -- >> 2.34.1 >>