From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtpout-03.galae.net (smtpout-03.galae.net [185.246.85.4]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4F2D23815DC for ; Sat, 25 Apr 2026 22:33:46 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.246.85.4 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1777156430; cv=none; b=eYfr3HOwZ031GwKH8ZxGTTHMIzi0ayJJG/Idw6GUYEuoNAXDSPEjFq3lK5g9GJIQYJBu3CMpyG9c2yyPbZHdQgYgQXJd8DSOCgsQ2oLsV4g1Yb2kDLvzH4sNdhFx8dhN+eAvfXFx1FJMkDNqFgwKdgtU15hFC1+o+316FvuKkvI= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1777156430; c=relaxed/simple; bh=3O/idcSEQhbKZA2ORBaOYYFCK/Eu+8saYV8LpBDquY4=; h=Message-ID:Date:MIME-Version:Subject:To:Cc:References:From: In-Reply-To:Content-Type; b=Gh3FfjQ6IdrLXd5VEZkK4dHM/SbcRO5syCUccrlIOTHu8jkg3hqoOOjMK+YqTkmxU06yMS6CADfxsC7m2uy0aw9GsfkI67TM9UxJLw9qUGo980/T6/Z8b3+wwybzO9vrsppfq/Dq+JgALwrstpw280s7ddfLhED6kjqrRhy3ylw= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com; spf=pass smtp.mailfrom=bootlin.com; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b=1wwlN62K; arc=none smtp.client-ip=185.246.85.4 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bootlin.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b="1wwlN62K" Received: from smtpout-01.galae.net (smtpout-01.galae.net [212.83.139.233]) by smtpout-03.galae.net (Postfix) with ESMTPS id A1DD04E42B16; Sat, 25 Apr 2026 22:33:44 +0000 (UTC) Received: from mail.galae.net (mail.galae.net [212.83.136.155]) by smtpout-01.galae.net (Postfix) with ESMTPS id 54FEF60535; Sat, 25 Apr 2026 22:33:44 +0000 (UTC) Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id 9934A10720E1B; Sun, 26 Apr 2026 00:33:37 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=dkim; t=1777156422; h=from:subject:date:message-id:to:cc:mime-version:content-type: content-transfer-encoding:content-language:in-reply-to:references; bh=iyX1v6azdkdyoxR/rRSogUNIumd7+kjCw9BTP8UqftE=; b=1wwlN62K28Y/yzGgXc1itDp3+LqtHGwxm+WAALwf5m4YPcT0r8AecTBHfP/4c9gowjcE1l TG91oh1Fu3nwnCznhmWJZ14b5eDRXSrlRAbBp9KIr8xEa88kJ+JkQVg+Ah447Znr/xbzkE UE3psEcVFkjCr9vtFCXRyWe+grS/WvSWB0VkOvta7BA1CgIutWkPcRCUZYCgH+LQqUNqoB ehmrwqGAs4JsPoGIKnSd3bjD0mpV7RSXoD1h/fbY7+R5rATamrnaZmHm+FNU3WmwjCR8iG KK1T4kAWVuuPX+F+CJa2yxw9VUDcnpQ4hubgHPs/r8UitsShoU+mvA+F/OcH7A== Message-ID: Date: Sun, 26 Apr 2026 00:32:53 +0200 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v3] drm/bridge: ti-sn65dsi83: add test pattern generation support To: Luca Ceresoli , Andrzej Hajda , Neil Armstrong , Robert Foss , Laurent Pinchart , Jonas Karlman , Jernej Skrabec , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Frieder Schrempf , Marek Vasut , Linus Walleij Cc: Hui Pu , Ian Ray , Thomas Petazzoni , dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org References: <20260416-ti-sn65dsi83-dual-lvds-fixes-and-test-pattern-v3-0-143886aebc6b@bootlin.com> <20260416-ti-sn65dsi83-dual-lvds-fixes-and-test-pattern-v3-1-143886aebc6b@bootlin.com> From: Louis Chauvet Content-Language: en-US In-Reply-To: <20260416-ti-sn65dsi83-dual-lvds-fixes-and-test-pattern-v3-1-143886aebc6b@bootlin.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-Last-TLS-Session-Version: TLSv1.3 On 4/16/26 15:59, Luca Ceresoli wrote: > Generation of a test pattern output is a useful tool for panel bringup and > debugging, and very simple to support with this chip. > > The value of REG_VID_CHA_ACTIVE_LINE_LENGTH_LOW needs to be divided by two > for the test pattern to work in dual LVDS mode. While not clearly stated in > the datasheet, this is needed according to the DSI Tuner [0] output. And > some dual-LVDS panels refuse to show any picture without this division by > two. > > [0] https://www.ti.com/tool/DSI-TUNER > > Signed-off-by: Luca Ceresoli > Reviewed-by: Louis Chauvet > --- > > Changes in v3: > - fixed incorrect halving of hdisplay in single-link mode > > Changes in v2: > - added local variable to avoid potential race condition leading to > inconsistent settings > --- > drivers/gpu/drm/bridge/ti-sn65dsi83.c | 14 ++++++++++++-- > 1 file changed, 12 insertions(+), 2 deletions(-) > > diff --git a/drivers/gpu/drm/bridge/ti-sn65dsi83.c b/drivers/gpu/drm/bridge/ti-sn65dsi83.c > index 17a885244e1e..2b6f6a54edb7 100644 > --- a/drivers/gpu/drm/bridge/ti-sn65dsi83.c > +++ b/drivers/gpu/drm/bridge/ti-sn65dsi83.c > @@ -114,6 +114,7 @@ > #define REG_VID_CHA_HORIZONTAL_FRONT_PORCH 0x38 > #define REG_VID_CHA_VERTICAL_FRONT_PORCH 0x3a > #define REG_VID_CHA_TEST_PATTERN 0x3c > +#define REG_VID_CHA_TEST_PATTERN_EN BIT(4) > /* IRQ registers */ > #define REG_IRQ_GLOBAL 0xe0 > #define REG_IRQ_GLOBAL_IRQ_EN BIT(0) > @@ -134,6 +135,9 @@ > #define REG_IRQ_STAT_CHA_SOT_BIT_ERR BIT(2) > #define REG_IRQ_STAT_CHA_PLL_UNLOCK BIT(0) > > +static bool sn65dsi83_test_pattern; > +module_param_named(test_pattern, sn65dsi83_test_pattern, bool, 0644); > + > enum sn65dsi83_channel { > CHANNEL_A, > CHANNEL_B > @@ -523,6 +527,7 @@ static void sn65dsi83_atomic_pre_enable(struct drm_bridge *bridge, > const struct drm_display_mode *mode; > struct drm_connector *connector; > struct drm_crtc *crtc; > + bool test_pattern = sn65dsi83_test_pattern; > bool lvds_format_24bpp; > bool lvds_format_jeida; > unsigned int pval; > @@ -645,7 +650,11 @@ static void sn65dsi83_atomic_pre_enable(struct drm_bridge *bridge, > REG_LVDS_LANE_CHB_LVDS_TERM : 0)); > regmap_write(ctx->regmap, REG_LVDS_CM, 0x00); > > - le16val = cpu_to_le16(mode->hdisplay); > + /* > + * Active line length needs to be halved for test pattern > + * generation in dual LVDS output. > + */ > + le16val = cpu_to_le16(mode->hdisplay / (test_pattern ? dual_factor : 1)); > regmap_bulk_write(ctx->regmap, REG_VID_CHA_ACTIVE_LINE_LENGTH_LOW, > &le16val, 2); > le16val = cpu_to_le16(mode->vdisplay); > @@ -668,7 +677,8 @@ static void sn65dsi83_atomic_pre_enable(struct drm_bridge *bridge, > (mode->hsync_start - mode->hdisplay) / dual_factor); > regmap_write(ctx->regmap, REG_VID_CHA_VERTICAL_FRONT_PORCH, > mode->vsync_start - mode->vdisplay); > - regmap_write(ctx->regmap, REG_VID_CHA_TEST_PATTERN, 0x00); > + regmap_write(ctx->regmap, REG_VID_CHA_TEST_PATTERN, > + test_pattern ? REG_VID_CHA_TEST_PATTERN_EN : 0); > > /* Enable PLL */ > regmap_write(ctx->regmap, REG_RC_PLL_EN, REG_RC_PLL_EN_PLL_EN); >