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Mon, 5 May 2025 17:14:51 +0000 Message-ID: Date: Mon, 5 May 2025 10:14:48 -0700 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v4 0/8] Support L3 Smart Data Cache Injection Allocation Enforcement (SDCIAE) To: "Luck, Tony" , "Moger, Babu" , "Babu Moger" , "tglx@linutronix.de" , "mingo@redhat.com" , "bp@alien8.de" , "dave.hansen@linux.intel.com" CC: "corbet@lwn.net" , "x86@kernel.org" , "hpa@zytor.com" , "akpm@linux-foundation.org" , "paulmck@kernel.org" , "rostedt@goodmis.org" , "thuth@redhat.com" , "ardb@kernel.org" , "gregkh@linuxfoundation.org" , "thomas.lendacky@amd.com" , "mario.limonciello@amd.com" , "perry.yuan@amd.com" , "seanjc@google.com" , "Huang, Kai" , "Li, Xiaoyao" , "kan.liang@linux.intel.com" , "riel@surriel.com" , "Li, Xin3" , "xin@zytor.com" , "Mehta, Sohil" , "ak@linux.intel.com" , "ebiggers@google.com" , "andrew.cooper3@citrix.com" , "gautham.shenoy@amd.com" , "Xiaojian.Du@amd.com" , "linux-doc@vger.kernel.org" , "linux-kernel@vger.kernel.org" , "james.morse@arm.com" , "fenghuay@nvidia.com" , "peternewman@google.com" References: <3e0e9b68-2ebe-40f8-a840-1ad7cd3f56e0@amd.com> <3ca0a5dc-ad9c-4767-9011-b79d986e1e8d@intel.com> From: Reinette Chatre Content-Language: en-US In-Reply-To: Content-Type: text/plain; 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That is the only constraint we need to think about >> here. I have repeatedly asked for IO alloc connection with CLOSIDs to not be exposed >> to user space (yet user documentation and messages to user space keeps doing so >> in this series). Support for IO alloc in this way is unique to AMD. We do not want >> resctrl to be constrained like this if another architecture needs to support >> some form of IO alloc and does so in a different way. > > This isn't unique to AMD. Intel also ties CLOSid to control features associated with > I/O (likewise with RMIDs for monitoring). > > See the Intel RDT architecture specification[1] chapter 4.4: > > " Non-CPU agent RDT uses the RMID and CLOS tags in the same way that they are used for CPU agents." As I understand AMD uses a single specific (the highest CLOSid supported by L3) CLOS that is then reserved for IO allocation. While both Intel and AMD technically "uses CLOSid", it is done differently, no? Specifically, is this documentation introduced in patch #5 accurate for Intel? + The feature routes the I/O traffic via specific CLOSID reserved + for io_alloc feature. By configuring the CBM (Capacity Bit Mask) + for the CLOSID, users can control the L3 portions available for + I/0 traffic. The reserved CLOSID will be excluded for group creation. Reinette