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([2a02:810d:15c0:828:d7cd:1be6:f89d:7218]) by smtp.gmail.com with ESMTPSA id gz4-20020a170907a04400b009571293d6acsm4248476ejc.59.2023.05.11.10.17.40 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 11 May 2023 10:17:41 -0700 (PDT) Message-ID: Date: Thu, 11 May 2023 19:17:39 +0200 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.11.0 Subject: Re: Need suggestions for smp related properties in cpus.yaml to support smpboot for cortex-r52 based platform Content-Language: en-US To: Ayan Kumar Halder , robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, matthias.bgg@gmail.com, angelogioacchino.delregno@collabora.com, geert+renesas@glider.be, magnus.damm@gmail.com, konrad.dybcio@linaro.org, andersson@kernel.org, mazziesaccount@gmail.com, conor.dooley@microchip.com, j@jannau.net, mailingradian@gmail.com, me@iskren.info, lpieralisi@kernel.org Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-renesas-soc@vger.kernel.org, Julien Grall , Stefano Stabellini , Michal Orzel , Michal Simek References: From: Krzysztof Kozlowski In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 11/05/2023 11:35, Ayan Kumar Halder wrote: > Hi Device Tree engineers, > > > Recently I have ported Xen on Cortex-R52 (AArch32-V8R processor) for our > AMD platform. > > I was discussing with xen-devel community about how we can properly > support smpboot when I was suggested that this might be the correct > forum for discussion. > > Please refer > https://lists.xenproject.org/archives/html/xen-devel/2023-05/msg00224.html > and the follow-ups for context. > > > The way smpboot works on our platform is as follows:- > > 1. core0 writes to register (say regA) the address of the secondary core > initialization routine. > > 2. core0 writes to another register (say regB) the value "0x1" to put > the secondary core in reset mode. > > 3. core0 writes to regB the value "0x0" to pull the secondary core out > of reset mode. > > regA, regB will differ for core1, core2, core3 and so on. > > > Currently, I am trying to bringup core1 only. > > > I am thinking to use "enable-method=spin-table" in the cpu node for > core1.  So that I can use "cpu-release-address" for regA. > > For regB, I am thinking of introducing a new property > "amd-cpu-reset-addr" in the cpu node. Propose a patch, that's how we discuss. Anyway as this is arm then you have a machine for your platform right? The address is not fixed? If the the regb is not a pen release-like, so you cannot use secondary-boot-reg, then check how other machines are doing it. Best regards, Krzysztof