From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-0.8 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, MAILING_LIST_MULTI,SPF_PASS,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id E036AC3279B for ; Wed, 4 Jul 2018 15:43:06 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 89C4321761 for ; Wed, 4 Jul 2018 15:43:06 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 89C4321761 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=arm.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752607AbeGDPnD (ORCPT ); Wed, 4 Jul 2018 11:43:03 -0400 Received: from foss.arm.com ([217.140.101.70]:39504 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752381AbeGDPnC (ORCPT ); Wed, 4 Jul 2018 11:43:02 -0400 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 9B5527A9; Wed, 4 Jul 2018 08:43:01 -0700 (PDT) Received: from [192.168.67.35] (usa-sjc-imap-foss1.foss.arm.com [10.72.51.249]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id A03BF3F5AD; Wed, 4 Jul 2018 08:42:59 -0700 (PDT) Subject: Re: [linux-sunxi] Re: [PATCH 0/2] Allwinner A64 timer workaround To: Thomas Gleixner Cc: Marc Zyngier , Daniel Lezcano , Samuel Holland , Maxime Ripard , Chen-Yu Tsai , Catalin Marinas , Will Deacon , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-sunxi@googlegroups.com, Mark Rutland References: <20180511022751.9096-1-samuel@sholland.org> <2c16d5ab-38f7-8f3e-875c-19e8032f440a@arm.com> <5283f98e-6443-db7a-fe51-6379ed19002c@arm.com> <24b78819-5e3f-431f-3987-f7409742ef07@linaro.org> <1d75c538-9166-5eec-a08c-b168f9770bd1@arm.com> <1a36f63c-0259-bdcd-bb96-d5230c2564ea@arm.com> <55fc9e48-6329-df75-3a12-60cc42d91a31@arm.com> From: Andre Przywara Openpgp: preference=signencrypt Autocrypt: addr=andre.przywara@arm.com; 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Linux x86_64; rv:52.0) Gecko/20100101 Thunderbird/52.8.0 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset=utf-8 Content-Language: en-GB Content-Transfer-Encoding: 7bit Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi, On 04/07/18 16:14, Thomas Gleixner wrote: > On Wed, 4 Jul 2018, Andre Przywara wrote: >> On 04/07/18 15:31, Thomas Gleixner wrote: >>> If that's the case then you need to find a different functional timer for >>> time keeping. Having an erratic behaving timer for time keeping is not an >>> option at all. >> >> That's not an option on arm64. There are other usable time sources in >> the SoC, but the arch timer is somewhat mandatory for all practical >> purposes on arm64. We rely on it in some many places that it's not >> feasible to run without it. That's why we call it "architected" timer >> after all ;-) > > The argument that it has to be used just because someone defined it as > 'architected' is bullshit and doesn't change the fact that it's broken and > not usable for timekeeping. There is no wiggle room. Either it works or > not, but works mostly is not an option. The "architected" part of the arch timer is fine, it's just that eventually someone has to implement that at some point. And as you mention below, this is where Murphy's law is kicking in ;-) Especially for such seemingly simple tasks as connecting a counter in the "uncore" part of the chip (Allwinner SoC) to the counter register interface in the core (ARM Cortex-A53) [1]. Apparently the propagation is not really atomic for all bits here ... >> But I am quite confident that we can find a correct workaround. Maybe >> it's really the TVAL (the downcounter) write which is the culprit here, >> since the hardware actually writes "now() + TVAL" into the CVAL >> (upcounter) register. This internal counter access may be flawed as well. > > If the write to the event device is wreckaging the counter which provides > time, then there is something seriously wrong either in the design or in > that particular piece of silicon. Apologies, that was my lousy wording: There is one 64-bit comparison register (CVAL), which signals when the counter (an independent register) is greater or equal. TVAL is just a different *view* of that same relation. So this part is fine, it's really that the "strictly monotonic counter" nature of CNTPCT is not really observed by the chip. > Yet another proof for the theory that timers are implemented by janitors > and that silicon/IP vendors have a competition running who can create the > most subtly broken timers. Intel surely had a head start with that, but ARM > is definitely catching up. ARM is trying really hard to be actually better ;-) Cheers, Andre. [1] http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0500g/BABIGHII.html