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[103.229.16.4]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-39668a5832bsm3060969a91.15.2026.08.26.00.48.49 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 26 Aug 2026 00:48:53 -0700 (PDT) Message-ID: Date: Wed, 26 Aug 2026 15:48:46 +0800 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH RESEND v5 21/25] drm/msm/dpu: use msm_dp_get_mst_intf_id() to get the intf id To: Dmitry Baryshkov Cc: Rob Clark , Dmitry Baryshkov , Abhinav Kumar , Sean Paul , Marijn Suijten , David Airlie , Simona Vetter , Jessica Zhang , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org, Abhinav Kumar References: <20260629-msm-dp-mst-v5-0-2ed6aee1867a@oss.qualcomm.com> <20260629-msm-dp-mst-v5-21-2ed6aee1867a@oss.qualcomm.com> Content-Language: en-US From: Yongxing Mou In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-Authority-Analysis: v=2.4 cv=a8AAM0SF c=1 sm=1 tr=0 ts=6a8e9a67 cx=c_pps a=0uOsjrqzRL749jD1oC5vDA==:117 a=nuhDOHQX5FNHPW3J6Bj6AA==:17 a=IkcTkHD0fZMA:10 a=Sv0fKeRqtYgA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=ZpdpYltYx_vBUK5n70dp:22 a=COk6AnOGAAAA:8 a=EUspDBNiAAAA:8 a=_xYO84BrWpCsddiSF-IA:9 a=QEXdDO2ut3YA:10 a=mQ_c8vxmzFEMiUWkPHU9:22 a=TjNXssC_j7lpFel5tvFf:22 X-Proofpoint-Spam-Info: AW1haW4tMjYwODI2MDA2MyBTYWx0ZWRfX8FJ4qEKJNeUE Pb0QnkbOj6U989PHPqNTXIhPOMjvA7ay+y6gJsEzNvka9KOyb8dRFInZT6/9on7U8pzDXlOSZKG zwZa0tLOM4AQ9eBsCK32cdWBr5Ug7Zs= X-Proofpoint-ORIG-GUID: ZcHBJw8hMAGR_rYp4T27qV-CSx4cQD6G X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwODI2MDA2MyBTYWx0ZWRfX3A6dLJGY6+2J 1jRlOwDfuFnM8Xo846/nX/TFgualdelH/zscEtOc6bB59goLleCWcO2WSoecOCLj0xdxHXTuEMH nydOW/q2I21XOOr4ZSLjPldY57ZtC5KXapLkmTfLBXPahVJj2YRtdDzsDKa9QAEVpIAoju2EsbU 3QY0MlKNrFDH3KtsekpnlHE8Riv7BzfusS/Un4CtQRqQPTXO8gDw6nGaX0T8/e/JTkNHsafoh3g yw8hg3NY0XELZkG4oFrpBmbDP7gQWoDWZl//ckkt9vU3pyNt0KSJWlfVtRTHW6KE3F5AT+nYMIX nzhC+AfS6jCC17qr/t9jlxderk+dg5T3rzU4sEwMKAfF6bBzWiOQcpwPvTeu4yf98xXR9L3DfsK L7Mmoe4i4O7a4IVBfCFXcR7w8t84aUiZRzhyf68p46iCx72geiiYL9QaOBoKxQ7I20FjygX4eOz uYsQvlPohsAF1x+PXow== X-Proofpoint-GUID: ZcHBJw8hMAGR_rYp4T27qV-CSx4cQD6G X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-08-26_02,2026-08-24_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 bulkscore=0 spamscore=0 lowpriorityscore=0 phishscore=0 adultscore=0 impostorscore=0 clxscore=1015 suspectscore=0 malwarescore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2608260063 On 7/13/2026 8:09 AM, Dmitry Baryshkov wrote: > On Mon, Jun 29, 2026 at 10:14:42PM +0800, Yongxing Mou wrote: >> Use msm_dp_get_mst_intf_id() to get the interface ID for the DP MST >> controller as the intf_id is unique for each MST stream of each DP >> controller. >> >> For DSI/eDP/DP SST, the stream_id is always 0, so existing behavior >> remains unchanged. >> >> Signed-off-by: Abhinav Kumar >> Signed-off-by: Yongxing Mou >> --- >> drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 20 +++++++++++--------- >> drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h | 2 ++ >> drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 4 ++++ >> 3 files changed, 17 insertions(+), 9 deletions(-) > > This really should have been a part (or done before) the patch adding > DPMST encoders. > Will splite this patch. >> >> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c >> index 1c74ff6f0dbd..3adfaeaab71d 100644 >> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c >> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c >> @@ -1438,18 +1438,21 @@ void dpu_encoder_phys_disable(struct drm_encoder *drm_enc, >> >> static struct dpu_hw_intf *dpu_encoder_get_intf(const struct dpu_mdss_cfg *catalog, >> struct dpu_rm *dpu_rm, >> - enum dpu_intf_type type, u32 controller_id) >> + struct msm_display_info *disp_info, u32 controller_id) > > As you are now passing whole msm_display_info, controller_id is > available as disp_info->h_tile_instance[i]. Pass index to this function > instead of passing controller_id. > > Ideally, split this patch into two: one changing the function to get > disp_info, another one adding stream_id to the struct. > >> { >> - int i = 0; >> + int i = 0, cnt = 0; >> + int stream_id = disp_info->stream_id; >> >> - if (type == INTF_WB) >> + if (disp_info->intf_type == INTF_WB) >> return NULL; >> >> + DPU_DEBUG("intf_type 0x%x controller_id %d stream_id %d\n", >> + disp_info->intf_type, controller_id, stream_id); >> for (i = 0; i < catalog->intf_count; i++) { >> - if (catalog->intf[i].type == type >> - && catalog->intf[i].controller_id == controller_id) { >> - return dpu_rm_get_intf(dpu_rm, catalog->intf[i].id); >> - } >> + if (catalog->intf[i].type == disp_info->intf_type && >> + controller_id == catalog->intf[i].controller_id) > > Why did you change the order of the args? > Hmm I'll restore the original argument order in the next revision. >> + if (cnt++ == stream_id) > > Squash into the condition. > Got it. >> + return dpu_rm_get_intf(dpu_rm, catalog->intf[i].id); >> } >> >> return NULL; >> @@ -2675,8 +2678,7 @@ static int dpu_encoder_setup_display(struct dpu_encoder_virt *dpu_enc, >> i, controller_id, phys_params.split_role); >> >> phys_params.hw_intf = dpu_encoder_get_intf(dpu_kms->catalog, &dpu_kms->rm, >> - disp_info->intf_type, >> - controller_id); >> + disp_info, controller_id); >> >> if (disp_info->intf_type == INTF_WB && controller_id < WB_MAX) >> phys_params.hw_wb = dpu_rm_get_wb(&dpu_kms->rm, controller_id); >> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h >> index 25ade3dbbeda..861d69afbd76 100644 >> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h >> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h >> @@ -28,6 +28,7 @@ >> * @h_tile_instance: Controller instance used per tile. Number of elements is >> * based on num_of_h_tiles >> * @is_cmd_mode Boolean to indicate if the CMD mode is requested >> + * @stream_id stream id for which the interface needs to be acquired >> * @vsync_source: Source of the TE signal for DSI CMD devices >> */ >> struct msm_display_info { >> @@ -35,6 +36,7 @@ struct msm_display_info { >> uint32_t num_of_h_tiles; >> uint32_t h_tile_instance[MAX_H_TILES_PER_DISPLAY]; >> bool is_cmd_mode; >> + int stream_id; >> enum dpu_vsync_source vsync_source; >> }; >> >> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c >> index 91d33b432427..b32ecd5b0777 100644 >> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c >> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c >> @@ -614,6 +614,7 @@ static int _dpu_kms_initialize_dsi(struct drm_device *dev, >> info.h_tile_instance[info.num_of_h_tiles++] = other; >> >> info.is_cmd_mode = msm_dsi_is_cmd_mode(priv->kms->dsi[i]); >> + info.stream_id = 0; > > It is memset to 0. Drop this (here and below). > Got it. >> >> rc = dpu_kms_dsi_set_te_source(&info, priv->kms->dsi[i]); >> if (rc) { >> @@ -689,6 +690,7 @@ static int _dpu_kms_initialize_displayport(struct drm_device *dev, >> } >> >> for (stream_id = 0; stream_id < stream_cnt; stream_id++) { >> + info.stream_id = stream_id; >> encoder = dpu_encoder_init(dev, DRM_MODE_ENCODER_DPMST, &info); >> if (IS_ERR(encoder)) { >> DPU_ERROR("encoder init failed for dp mst display\n"); >> @@ -716,6 +718,7 @@ static int _dpu_kms_initialize_hdmi(struct drm_device *dev, >> info.num_of_h_tiles = 1; >> info.h_tile_instance[0] = 0; >> info.intf_type = INTF_HDMI; >> + info.stream_id = 0; >> >> encoder = dpu_encoder_init(dev, DRM_MODE_ENCODER_TMDS, &info); >> if (IS_ERR(encoder)) { >> @@ -748,6 +751,7 @@ static int _dpu_kms_initialize_writeback(struct drm_device *dev, >> /* use only WB idx 2 instance for DPU */ >> info.h_tile_instance[0] = wb_idx; >> info.intf_type = INTF_WB; >> + info.stream_id = 0; >> >> maxlinewidth = dpu_rm_get_wb(&dpu_kms->rm, info.h_tile_instance[0])->caps->maxlinewidth; >> >> >> -- >> 2.43.0 >> >