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[103.229.16.4]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2b08366c443sm145231065ad.56.2026.03.23.07.09.13 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 23 Mar 2026 07:09:17 -0700 (PDT) Message-ID: Date: Mon, 23 Mar 2026 22:09:08 +0800 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2] arm64: dts: qcom: glymur: add coresight nodes To: Bjorn Andersson Cc: Konrad Dybcio , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Tingwei Zhang , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org References: <20260318-add-coresight-dt-nodes-for-glymur-v2-1-d76e08f21fa5@oss.qualcomm.com> <7972211e-d735-4401-ada9-b83c7b96b612@oss.qualcomm.com> Content-Language: en-US From: Jie Gan In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit X-Authority-Analysis: v=2.4 cv=b+q/I9Gx c=1 sm=1 tr=0 ts=69c1498f cx=c_pps a=cmESyDAEBpBGqyK7t0alAg==:117 a=nuhDOHQX5FNHPW3J6Bj6AA==:17 a=IkcTkHD0fZMA:10 a=Yq5XynenixoA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=ZpdpYltYx_vBUK5n70dp:22 a=EUspDBNiAAAA:8 a=vii5j4Xdnaj1KWSRWHEA:9 a=3ZKOabzyN94A:10 a=QEXdDO2ut3YA:10 a=1OuFwYUASf3TG4hYMiVC:22 X-Proofpoint-ORIG-GUID: xCU4hQVZP6Z8PIfcnmUfKKa7y1al-ysE X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwMzIzMDEwOSBTYWx0ZWRfX+6jklhOvZP5u qtIos+OE/oPUEYGx2OUrS5jCLg0isBzab8vsTvL76+YiBqKHEYtbyI9TaDtDmVSepisRSLA9ewA fMTlZ9mIU4d4lUlVSg+1FT4JXcg9khjEmORHI6+SWp5IjN1mw+1NAlz07bCbjjTsTE9meHZ0MI3 y9QORkpFWJ+EbEBZEx7FkJWCNW2H33fN91bpSTl3PzYv8ST1zh9c9X9sdKfXt6NkboXGwK73ANA 6eqxU3SkvkMjbAk5E/cXj0vrovcqTaZWgTmUN0e2IXRJdMfA0W2g4BFEHG8OYdJzuTdqEOAkbJl Jm8KgMQGdGjZHcJ+H8mDe61E6EUfMskf7sUoVBFdyVeHOzywC9ZfJaiVn0pwcwHazAGSB4Gwwag zAPS+RyDdOOUPezHGKbg2uv9qIENHisnNx3uSLVaWTiPf4lopYONY13Ol3XVF/VI1P13y5sYlu4 Mj/aJ3yncGtbT6zHmrw== X-Proofpoint-GUID: xCU4hQVZP6Z8PIfcnmUfKKa7y1al-ysE X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-03-23_04,2026-03-23_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 lowpriorityscore=0 impostorscore=0 adultscore=0 malwarescore=0 bulkscore=0 suspectscore=0 phishscore=0 clxscore=1015 spamscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2603050001 definitions=main-2603230109 On 3/23/2026 10:03 PM, Bjorn Andersson wrote: > On Mon, Mar 23, 2026 at 09:27:41PM +0800, Jie Gan wrote: >> >> >> On 3/23/2026 9:02 PM, Konrad Dybcio wrote: >>> On 3/23/26 1:30 PM, Jie Gan wrote: >>>> >>>> >>>> On 3/23/2026 7:05 PM, Konrad Dybcio wrote: >>>>> On 3/18/26 12:42 PM, Jie Gan wrote: >>>>>> Add CoreSight nodes to enable trace paths like TPDM->ETF/STM->ETF. >>>>>> These devices are part of the AOSS, CDSP, QDSS, PCIe5, TraceNoc and >>>>>> some small subsystems, such as GCC, IPCC, PMU and so on. >>>>>> >>>>>> Signed-off-by: Jie Gan >>>>>> --- >>>>>> Changes in V2: >>>>>> 1. removed two cti devices due to GFX block is down >>>>> >>>>> i.e. "because GPU is not yet enabled"? >>>> >>>> Yeah, these CTI devices have clock issue for enabling due to the GPU block is not yet enabled. >>> >>> Do they need the GPU to be online, or a clock from GPU_CC, or >>> maybe something else? >> >> We need a specific debug clock inside the GPU block. The debug clock only >> can be enabled while GPU is online. > > What happens once GPU has been delivered, but for some reason is > inactive and we try to use this CTI device? We will check these devices again once GPU is available. We also will cross check with AOP team if there is a clock enable/disable requirement with the specific debug clock. > >> Also needs AOP to support enable/disable >> the debug clock. >> > > When you hit such dependencies, please write and contribute the patch > (in this case, you can do it in a separate patch/series). > noted. The capability to enable/disable debug clocks is supported by mproc dt nodes(aoss_qmp). It will send message to AOP core to enable debug clocks by configuring a specific register in AOP via mailbox. Thanks, Jie > Regards, > Bjorn > >>> >>>>>>     - cti@11c42000 >>>>>>     - cti@11c4b000 >>>>>> 2. changes two TPDM devices to static: >>>>>>     - tpdm-cdsp-cmsr >>>>>>     - tpdm-cdsp-cmsr2 >>>>> >>>>> They were TPDM instances in v1. What's the reason for the change? >>>> >>>> These TPDMs havent clock source for accessing registers. We only need enable its ports to output trace data. So I have changed them to static-TPDM compatible. >>> >>> The registers are clearly physically there. Are you saying that we >>> (currently?) can't enable the clock required to access them? Or is >>> there a design defect that's preventing us from doing so? >> >> It's about hardware design. Some of the TPDM devices are designed as static, >> means we dont need access the register of the device for configuring. The >> trace data of the static TPDM is enabled by default, we only need enable the >> port of the connected TPDA device for receiving the data. >> >> I have tested these devices with Jtag attached, so I didnt observe issue >> about these new devices in the CDSP block. (Jtag will provide debug >> capability for all debug devices) Also cross-checked with hardware team for >> confirming these devices are working as static. >> >> Thanks, >> Jie >> >>> >>> Konrad >>> >>