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charset=UTF-8 Content-Transfer-Encoding: 7bit X-Proofpoint-GUID: BhO7t-tINdZZCoGlOr93PaT_3IUTIUHT X-Proofpoint-ORIG-GUID: BhO7t-tINdZZCoGlOr93PaT_3IUTIUHT X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwODA2MDAwOSBTYWx0ZWRfX/i+dIs6/7eBj EsyKWvqd/aQvvzsMcvnMKfF1AZ6KyViJWqgD7bHY78biFNFiILggugcVaoYrYqPHem8rP4pLNFq /a5noFbeaw2TtEOsypG8R/renkGAoN58d0AQk1BEkMZitZ31tZtKYScUzguVSGpjWD6pma2HZO4 lcoMEo8yyI3C5QBtbX0g3NExy6LYrmh2k1paRTerPYv7nJ/Z9xqRH2OLvXLnySuiTTg3+c8Udox rRiAGXW3YFzWjYhtYV+oIkYmcSJW9ahGtHMyJy9XuYanyWFSLR2+0irgbfqk2KANUQ/iW281tZE yy+OGhdy6cbJ5vCb6zdb3QIxr9ew0W5HarpBXEKOM9bpd0yDc3FFplWSAsf2E8B+vVMLp1GYAvs WtVoHtYp X-Authority-Analysis: v=2.4 cv=GrlC+l1C c=1 sm=1 tr=0 ts=6895c95a cx=c_pps a=Oh5Dbbf/trHjhBongsHeRQ==:117 a=fChuTYTh2wq5r3m49p7fHw==:17 a=IkcTkHD0fZMA:10 a=2OwXVqhp2XgA:10 a=EUspDBNiAAAA:8 a=zhkC1EFh2bCrlkiyJb0A:9 a=QEXdDO2ut3YA:10 a=_Vgx9l1VpLgwpw_dHYaR:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-08-08_02,2025-08-06_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 malwarescore=0 clxscore=1015 suspectscore=0 priorityscore=1501 phishscore=0 adultscore=0 bulkscore=0 impostorscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2507300000 definitions=main-2508060009 On 8/7/2025 6:37 PM, Konrad Dybcio wrote: > On 8/6/25 12:21 PM, Taniya Das wrote: >> >> >> On 8/6/2025 3:34 PM, Konrad Dybcio wrote: >>> On 8/4/25 4:21 PM, Taniya Das wrote: >>>> >>>> >>>> On 8/4/2025 6:40 PM, Konrad Dybcio wrote: >>>>> On 8/4/25 11:00 AM, Taniya Das wrote: >>>>>> >>>>>> >>>>>> On 8/1/2025 5:24 PM, Konrad Dybcio wrote: >>>>>>> On 8/1/25 7:31 AM, Abel Vesa wrote: >>>>>>>> On 25-08-01 10:02:15, Taniya Das wrote: >>>>>>>>> >>>>>>>>> >>>>>>>>> On 7/30/2025 4:55 PM, Abel Vesa wrote: >>>>>>>>>> On 25-07-29 11:12:37, Taniya Das wrote: >>>>>>>>>>> Add a clock driver for the TCSR clock controller found on Glymur, which >>>>>>>>>>> provides refclks for PCIE, USB, and UFS. >>>>>>>>>>> >>>>>>>>>>> Signed-off-by: Taniya Das >>>>>>>>>>> --- >>>>>>>>>>> drivers/clk/qcom/Kconfig | 8 ++ >>>>>>>>>>> drivers/clk/qcom/Makefile | 1 + >>>>>>>>>>> drivers/clk/qcom/tcsrcc-glymur.c | 257 +++++++++++++++++++++++++++++++++++++++ >>>>>>>>>>> 3 files changed, 266 insertions(+) >>>>>>>>>>> >>>>>>>>>> >>>>>>>>>> [...] >>>>>>>>>> >>>>>>>>>>> + >>>>>>>>>>> +static struct clk_branch tcsr_edp_clkref_en = { >>>>>>>>>>> + .halt_reg = 0x1c, >>>>>>>>>>> + .halt_check = BRANCH_HALT_DELAY, >>>>>>>>>>> + .clkr = { >>>>>>>>>>> + .enable_reg = 0x1c, >>>>>>>>>>> + .enable_mask = BIT(0), >>>>>>>>>>> + .hw.init = &(const struct clk_init_data) { >>>>>>>>>>> + .name = "tcsr_edp_clkref_en", >>>>>>>>>>> + .ops = &clk_branch2_ops, >>>>>>>>>> >>>>>>>>>> As discussed off-list, these clocks need to have the bi_tcxo as parent. >>>>>>>>>> >>>>>>>>>> Otherwise, as far as the CCF is concerned these clocks will have rate 0, >>>>>>>>>> which is obviously not the case. >>>>>>>>>> >>>>>>>>>> Bringing this here since there is a disconnect between X Elite and >>>>>>>>>> Glymur w.r.t this now. >>>>>>>>> >>>>>>>>> >>>>>>>>> The ref clocks are not required to be have a parent of bi_tcxo as these >>>>>>>>> ideally can be left enabled(as a subsystem requirement) even if HLOS >>>>>>>>> (APSS) goes to suspend. With the bi_tcxo parent the ARC vote from >>>>>>>>> HLOS/APSS will not allow APSS to collapse. >>>>>>>> >>>>>>>> Is there a scenario where the APSS is collapsed and still the ref clock >>>>>>>> needs to stay enabled ? Sorry, this doesn't make sense to me. >>>>>>> >>>>>>> MDSS is capable of displaying things from a buffer when the CPU is off, >>>>>>> AFAICU >>>>>>> >>>>>>> We can do CXO_AO instead to have it auto-collapse if it's just Linux >>>>>>> requesting it to stay on, I think. >>>>>>> >>>>>> >>>>>> Thanks Konrad for adding the display use case. >>>>>> Abel, we earlier also had some PCIe, USB use cases where we had to leave >>>>>> the ref clocks ON and APSS could collapse. >>>>> >>>>> XO votes will prevent CX collapse, not APSS collapse. CX also powers >>>>> USB and PCIe so that only makes sense. >>>>> >>>>> I think it's fair to just stick XO as the parent of every refclock >>>>> today and think about the what-ifs (such as the mdss case I mentioned >>>>> above) later - especially since we have no infra to take full advantage >>>>> of it today (non-APSS RSCs etc.) >>>>> >>>> >>>> When ref clock have been part of GCC, then also they didn't have any xo >>>> as the parent, similar design we kept when it was moved to TCSR as well. >>> >>> Perhaps we've been running on luck (i.e. XO votes being cast through >>> another device / clock as a second order effect) all this time.. I'd >>> happily move towards formal correctness. >>> >> >> I would like to stay with no XO linkage to TCSR. Any driver has specific >> XO requirement should vote for the rpmhcc XO or XO_AO. > > Every driver has an XO requirement, as we happen not to have any > other crystals onboard.. The clock plan says that these refclks > are direct children of XO too > The refclocks are just not the direct XO, there could be other source as well. But I am okay to add the XO parent if it helps the use case on X Elite and then following use cases on Glymur. I will add the XO parent in the next patchset. -- Thanks, Taniya Das