From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from PH8PR06CU001.outbound.protection.outlook.com (mail-westus3azon11012025.outbound.protection.outlook.com [40.107.209.25]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 694DA3F9FB; Thu, 26 Feb 2026 00:09:41 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=40.107.209.25 ARC-Seal:i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1772064582; cv=fail; b=jzTOQxnoaBQaAtsQH+Ke3kaA40pVRp0hLazf4OCA7i7JOMd1EF9RgsM2EiomeqIosJYEWISYlHDgRjwJEQLc1bTx/lKctiocxJfLt/Tgudl8858tjTajL/2fQ+NZLFKjXa8pwHLgxHafA7crgtTJ9po6nLHaxre5V4LkbjpWdj4= ARC-Message-Signature:i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1772064582; c=relaxed/simple; bh=g8MPRqsc+Yu2M26EoixHnFh9MdBdZSiuI8ismCNQRuc=; h=Message-ID:Date:Subject:To:Cc:References:From:In-Reply-To: Content-Type:MIME-Version; b=UGQM3KYKrGXa00h12Y6BAfyuD9QfIJJfjBY2TQFmJpu8Ns/uBplxokMOhjdb4id4EwGAxw7pRKjI3dyNZctX+3vdd9YtptTFeEGqmGLK2+O5WryjkCy5tlVKPdT2vjpNXDAJTgO2aoTcncq8cBiyC3shanEGTXdLGbt5pXoWSmo= ARC-Authentication-Results:i=2; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=amd.com; spf=fail smtp.mailfrom=amd.com; dkim=pass (1024-bit key) header.d=amd.com header.i=@amd.com header.b=Y9wqBRkp; arc=fail smtp.client-ip=40.107.209.25 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=amd.com Authentication-Results: smtp.subspace.kernel.org; spf=fail smtp.mailfrom=amd.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=amd.com header.i=@amd.com header.b="Y9wqBRkp" ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=rYClGokGUB1q/W6zjMbkOGKNCJyzAHOOp3uB0+DpQO4lVkmnmHQ6XR4h0EqSmii2rpemzXcPo9yZo+u7qFmjIF1Ei3j8OFsCHVUt2arM9n/kUfTs9LwwTB2TLMpX4Dtujy/+xooLGAFKmjF44QqjAy3NzZbMF7KUI/b4+0oVyoyK26FsehPL9JcBxoz88tA86LJw+uWg+dyJmgZ6Rjl8liacI4oFvUyqoLqxvayJB27eD7NNG/VKs0VynnGT32JcHoKCgpoLxkpyhz+DtYQ9U4l8q6GJ+U0wA5MRJePRuh9zg6QSiYgHj6IaaXxevL3HCR3cwKiH0x5iS3ps8EiJxQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=jes4leqCxTCiCFuzCU++gW72f0gEYBeaZWmcpoOHG/c=; b=Q4KKdR3Xj6UETzClKgeFtRc61l7oth4QxLuwwyQkrxvEIu43VvLY67gJ/CcQR4MMjDP0c+CSBXN4YkN1Cbatq0Qah2ZRsDcKYfJVlPpiFeNJQKvzC2A4JQcYutVtjCTaF0eeH41HbOn6DMFUbJ9fzpnU7Ar0WM4VDHowmvU9oiEOoebVtMvKFNL85mPPjI7GVxr35QZitQlJ8rugSqE95TdFoIWAEnL9kPXPe+1fleUMWLiGMkAlNxgck2EJ1K4AgV9NvH7xzYONif98pUihKozfGJrsqVzLt7gWSV1gpx9254qbDQTSYBjzHTdPRlp7HBMhLyjD78+YKbpYaMxOzA== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=amd.com; dmarc=pass action=none header.from=amd.com; dkim=pass header.d=amd.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amd.com; s=selector1; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=jes4leqCxTCiCFuzCU++gW72f0gEYBeaZWmcpoOHG/c=; b=Y9wqBRkpnwBVsClt2pCU26iPS63BWla+LSuzPzlXNJ1gRns5af2WsdVC3GFtVyFpRwL/uxKP3NmthN7ooRhMOHeA78/1Cq9SsgVd9qdegO/tPzFJVHFELjU4PUFPE3IZREzw550MExoZu9vbaLmYlPKksF6bWvXRAjCRaWFKuDk= Authentication-Results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=amd.com; Received: from CH3PR12MB9194.namprd12.prod.outlook.com (2603:10b6:610:19f::7) by SA1PR12MB7222.namprd12.prod.outlook.com (2603:10b6:806:2bf::15) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9632.22; Thu, 26 Feb 2026 00:09:32 +0000 Received: from CH3PR12MB9194.namprd12.prod.outlook.com ([fe80::1e6b:ca8b:7715:6fee]) by CH3PR12MB9194.namprd12.prod.outlook.com ([fe80::1e6b:ca8b:7715:6fee%4]) with mapi id 15.20.9654.007; Thu, 26 Feb 2026 00:09:32 +0000 Message-ID: Date: Thu, 26 Feb 2026 11:09:11 +1100 User-Agent: Mozilla Thunderbird Beta Subject: Re: [PATCH kernel 1/9] pci/tsm: Add TDISP report blob and helpers to parse it To: dan.j.williams@intel.com, x86@kernel.org Cc: linux-kernel@vger.kernel.org, kvm@vger.kernel.org, linux-pci@vger.kernel.org, Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen , "H. Peter Anvin" , Sean Christopherson , Paolo Bonzini , Andy Lutomirski , Peter Zijlstra , Bjorn Helgaas , Marek Szyprowski , Robin Murphy , Andrew Morton , Catalin Marinas , Michael Ellerman , Mike Rapoport , Tom Lendacky , Ard Biesheuvel , Neeraj Upadhyay , Ashish Kalra , Stefano Garzarella , Melody Wang , Seongman Lee , Joerg Roedel , Nikunj A Dadhania , Michael Roth , Suravee Suthikulpanit , Andi Kleen , Kuppuswamy Sathyanarayanan , Tony Luck , David Woodhouse , Greg Kroah-Hartman , Denis Efremov , Geliang Tang , Piotr Gregor , "Michael S. Tsirkin" , Alex Williamson , Arnd Bergmann , Jesse Barnes , Jacob Pan , Yinghai Lu , Kevin Brodsky , Jonathan Cameron , "Aneesh Kumar K.V (Arm)" , Xu Yilun , Herbert Xu , Kim Phillips , Konrad Rzeszutek Wilk , Stefano Stabellini , Claire Chang , linux-coco@lists.linux.dev, iommu@lists.linux.dev References: <20260225053806.3311234-1-aik@amd.com> <20260225053806.3311234-2-aik@amd.com> <699e93db9ad47_1cc510090@dwillia2-mobl4.notmuch> From: Alexey Kardashevskiy Content-Language: en-US In-Reply-To: <699e93db9ad47_1cc510090@dwillia2-mobl4.notmuch> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-ClientProxiedBy: SY5P282CA0056.AUSP282.PROD.OUTLOOK.COM (2603:10c6:10:20a::18) To CH3PR12MB9194.namprd12.prod.outlook.com (2603:10b6:610:19f::7) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CH3PR12MB9194:EE_|SA1PR12MB7222:EE_ X-MS-Office365-Filtering-Correlation-Id: 62eb64fa-c046-4b11-9163-08de74cb5157 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|7416014|376014|366016|1800799024|7053199007; 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The report enumerates >> MMIO resources and their properties which will take effect upon >> transitioning to the RUN state. >> >> Store the report in pci_tsm. >> >> Define macros and helpers to parse the binary blob. >> >> Signed-off-by: Alexey Kardashevskiy >> --- >> >> Probably pci_tsm::report could be struct tdi_report_header*? > [..] >> +struct tdi_report_header { >> + __u16 interface_info; /* TSM_TDI_REPORT_xxx */ >> + __u16 reserved2; >> + __u16 msi_x_message_control; >> + __u16 lnr_control; >> + __u32 tph_control; >> + __u32 mmio_range_count; >> +} __packed; >> + >> +/* >> + * Each MMIO Range of the TDI is reported with the MMIO reporting offset added. >> + * Base and size in units of 4K pages >> + */ >> +#define TSM_TDI_REPORT_MMIO_MSIX_TABLE BIT(0) >> +#define TSM_TDI_REPORT_MMIO_PBA BIT(1) >> +#define TSM_TDI_REPORT_MMIO_IS_NON_TEE BIT(2) >> +#define TSM_TDI_REPORT_MMIO_IS_UPDATABLE BIT(3) >> +#define TSM_TDI_REPORT_MMIO_RESERVED GENMASK(15, 4) >> +#define TSM_TDI_REPORT_MMIO_RANGE_ID GENMASK(31, 16) >> + >> +struct tdi_report_mmio_range { >> + __u64 first_page; /* First 4K page with offset added */ >> + __u32 num; /* Number of 4K pages in this range */ >> + __u32 range_attributes; /* TSM_TDI_REPORT_MMIO_xxx */ > > Those should be __le64 and le32, right? Oh yes. > But see below for another > option... > >> +} __packed; >> + >> +struct tdi_report_footer { >> + __u32 device_specific_info_len; >> + __u8 device_specific_info[]; >> +} __packed; >> + >> +#define TDI_REPORT_HDR(rep) ((struct tdi_report_header *) ((rep)->data)) >> +#define TDI_REPORT_MR_NUM(rep) (TDI_REPORT_HDR(rep)->mmio_range_count) >> +#define TDI_REPORT_MR_OFF(rep) ((struct tdi_report_mmio_range *) (TDI_REPORT_HDR(rep) + 1)) >> +#define TDI_REPORT_MR(rep, rangeid) TDI_REPORT_MR_OFF(rep)[rangeid] >> +#define TDI_REPORT_FTR(rep) ((struct tdi_report_footer *) &TDI_REPORT_MR((rep), \ >> + TDI_REPORT_MR_NUM(rep))) >> + > > So we all have a version of a patch like this and the general style > suggestion I have is to just parse this layout with typical > offsets+bitfield definitions. > > This follows the precedent, admittedly tiny, of the DOE definitions in > pci_regs.h. See: > > /* DOE Data Object - note not actually registers */ > > I have a patch that parses the TDISP report with these defines: > > /* > * PCIe ECN TEE Device Interface Security Protocol (TDISP) > * > * Device Interface Report data object layout as defined by PCIe r7.0 section > * 11.3.11 > */ > #define PCI_TSM_DEVIF_REPORT_INFO 0 > #define PCI_TSM_DEVIF_REPORT_MSIX 4 > #define PCI_TSM_DEVIF_REPORT_LNR 6 > #define PCI_TSM_DEVIF_REPORT_TPH 8 > #define PCI_TSM_DEVIF_REPORT_MMIO_COUNT 12 > #define PCI_TSM_DEVIF_REPORT_MMIO_PFN 0 /* An interface report 'pfn' is 4K in size */ > #define PCI_TSM_DEVIF_REPORT_MMIO_NR_PFNS 8 > #define PCI_TSM_DEVIF_REPORT_MMIO_ATTR 12 I cannot easily see from these what the sizes are. And how many of each. > #define PCI_TSM_DEVIF_REPORT_MMIO_ATTR_MSIX_TABLE BIT(0) > #define PCI_TSM_DEVIF_REPORT_MMIO_ATTR_MSIX_PBA BIT(1) > #define PCI_TSM_DEVIF_REPORT_MMIO_ATTR_IS_NON_TEE BIT(2) > #define PCI_TSM_DEVIF_REPORT_MMIO_ATTR_IS_UPDATABLE BIT(3) > #define PCI_TSM_DEVIF_REPORT_MMIO_ATTR_RANGE_ID GENMASK(31, 16) > #define PCI_TSM_DEVIF_REPORT_MMIO_SIZE (16) > #define PCI_TSM_DEVIF_REPORT_BASE_SIZE(nr_mmio) (16 + nr_mmio * PCI_TSM_DEVIF_REPORT_MMIO_SIZE) > > Any strong feelings one way or the other? I have a mild preference for > this offset+bitfields approach. My variant is just like this (may be need to put it in the comment): tdi_report_header tdi_report_mmio_range[] tdi_report_footer imho easier on eyes. I can live with either if the majority votes for it. Thanks. -- Alexey