From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D76EBC4332F for ; Thu, 20 Oct 2022 10:46:41 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230085AbiJTKqk (ORCPT ); Thu, 20 Oct 2022 06:46:40 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:32952 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229491AbiJTKqi (ORCPT ); Thu, 20 Oct 2022 06:46:38 -0400 Received: from mail.3ffe.de (0001.3ffe.de [IPv6:2a01:4f8:c0c:9d57::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A66AD1C5E30 for ; Thu, 20 Oct 2022 03:46:36 -0700 (PDT) Received: from 3ffe.de (0001.3ffe.de [IPv6:2a01:4f8:c0c:9d57::1]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by mail.3ffe.de (Postfix) with ESMTPSA id 1D88E1285; Thu, 20 Oct 2022 12:46:34 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=walle.cc; s=mail2022082101; t=1666262794; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=qyfpMJ7wvOKQzKJbA8gxhqaiUcCTequz7kYwWgzsxo4=; b=S8juV9ehFY1QtzfsNES16OBDCJDt6D8JuIVPz/Los2OyZjJ6w3Vjia8HTvNhkenO54ppQ3 unFA6yGNnUmRezw+llCgvp6smheHSUdl+nLDaH/sj86RcbiqSsEZMzD2eIy8tN7mbXeIk/ rEWjea8uO3QWs23LC7Oxzl3f9pzXOV512GMQEH8dcbHm6NY4EV7MmMCrEr3pbu3X1tRbg9 zyPNP/obX07WdBHsRY4cKH4ZJpxA9GVSIXWnwqmoYx6tk/JL+2H54ovBwMfEH+I55genyJ Q2YoIew+XpV+wQ38hPNvT32jFOsu9aTsY6KekRcOm4EUF9UMJ+FWfU4cKphlkA== MIME-Version: 1.0 Date: Thu, 20 Oct 2022 12:46:33 +0200 From: Michael Walle To: Eliav Farber Cc: tudor.ambarus@microchip.com, pratyush@kernel.org, miquel.raynal@bootlin.com, richard@nod.at, vigneshr@ti.com, linux-mtd@lists.infradead.org, linux-kernel@vger.kernel.org, talel@amazon.com, jonnyc@amazon.com, hhhawa@amazon.com, hanochu@amazon.com, itamark@amazon.com, shellykz@amazon.com, amitlavi@amazon.com, dkl@amazon.com Subject: Re: [PATCH v3 1/1] mtd: spi-nor: micron-st: Enable locking for mt25qu256a In-Reply-To: <20221020092058.33844-1-farbere@amazon.com> References: <20221020092058.33844-1-farbere@amazon.com> User-Agent: Roundcube Webmail/1.4.13 Message-ID: X-Sender: michael@walle.cc Content-Type: text/plain; charset=US-ASCII; format=flowed Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Am 2022-10-20 11:20, schrieb Eliav Farber: > mt25qu256a [1] uses the 4 bit Block Protection scheme and supports > Top/Bottom protection via the BP and TB bits of the Status Register. > BP3 is located in bit 6 of the Status Register. > Tested on MT25QU256ABA8ESF-0SIT. > > [1] > https://www.micron.com/-/media/client/global/documents/products/data-sheet/nor-flash/serial-nor/mt25q/die-rev-a/mt25q_qljs_u_256_aba_0.pdf > > Signed-off-by: Eliav Farber > Link: > https://lore.kernel.org/lkml/20221019071631.15191-1-farbere@amazon.com Reviewed-by: Michael Walle Thanks, -michael