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[103.229.16.4]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2dafe929d77sm11790525ad.39.2026.09.03.08.06.55 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 03 Sep 2026 08:07:01 -0700 (PDT) Message-ID: Date: Thu, 3 Sep 2026 23:06:53 +0800 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v3 04/12] clk: qcom: ipq-cmn-pll: Register CMN PLL /2 clock To: Abel Vesa Cc: Bjorn Andersson , Michael Turquette , Stephen Boyd , Brian Masney , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Konrad Dybcio , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, quic_kkumarcs@quicinc.com, quic_linchen@quicinc.com, quic_leiwei@quicinc.com, quic_suruchia@quicinc.com References: <20260814-qcom_ipq5210_cmnpll-v3-0-21c3db378611@oss.qualcomm.com> <20260814-qcom_ipq5210_cmnpll-v3-4-21c3db378611@oss.qualcomm.com> Content-Language: en-US From: Jie Luo In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Proofpoint-ORIG-GUID: Bvt2hYMXkgS-qVLibwnbfnCjjPS6f-P5 X-Proofpoint-Spam-Info: AW1haW4tMjYwOTAzMDEzMiBTYWx0ZWRfXy6e41LXhWCbZ jB1p5xNoQ+ncwKeOhiXphzm8ElvnIzVqwfZnYLyZ89tngf3/38TcR33allZe8nMHdnhozZ9sIck RoVX/w+UnJIMx38C57MMganZGI+erWY= X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwOTAzMDEzMiBTYWx0ZWRfX9B+9nBf0sgKR 0DX1mLEZ6gtqggqqNpZXHM/Yo8CcD5YmKsuwJWWWOSVfpC/SDbWUyg8fqHar8H5Q3VJeDJ7lzok YK51VS+Mrw5r/imvhPyOmTU3nFlHWlhxk+b6/Ik0Ps0/1AyIiaEHcyoVaxMtXa5c6qoTeQOJABM Xud4irhTDlyRMNAPTVSh1Fq1P78w7jw/3dD713l7drfIXJQGORmCLd+6p7xhRjuy7H+AMXU+ZQe Jxfrlky6zKe1AtxWo9pt8+8hdDzXPttA00ra0rErODheFjkw3ftYDVvrYmHkN8VZcnDen3iLodM vYvMUi3DdYuQbu/i0k0by+DeFYMsNwVXG8pUg45wnPNKGzE+vdMYAE6HBGkZ85YQPa+cLDuXSOT p73IXMouQamQXCTSUUD2aLI+5jVbO6aWbwhQJY4qAleA+CqInM5jLExc06yDwiOvx1qw+DtvbpW x61CA5B1Yy0XahWq6zw== X-Authority-Analysis: v=2.4 cv=NNTlPU6g c=1 sm=1 tr=0 ts=6a998d17 cx=c_pps a=cmESyDAEBpBGqyK7t0alAg==:117 a=nuhDOHQX5FNHPW3J6Bj6AA==:17 a=IkcTkHD0fZMA:10 a=VdqzKS8jKosA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=eoimf2acIAo5FJnRuUoq:22 a=EUspDBNiAAAA:8 a=_0NKdZRjI3JEYUyFDiwA:9 a=QEXdDO2ut3YA:10 a=1OuFwYUASf3TG4hYMiVC:22 X-Proofpoint-GUID: Bvt2hYMXkgS-qVLibwnbfnCjjPS6f-P5 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-09-03_04,2026-09-03_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 phishscore=0 lowpriorityscore=0 spamscore=0 bulkscore=0 adultscore=0 malwarescore=0 clxscore=1015 suspectscore=0 impostorscore=0 priorityscore=1501 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2609030132 On 9/3/2026 9:18 PM, Abel Vesa wrote: > On 26-08-14 05:48:14, Luo Jie wrote: >> Most CMN PLL output clocks are derived from the 12 GHz PLL output >> through a shared, physical /2 stage, ahead of any further per-clock >> processing: a gated fixed rate (PCS/ETH0/ETH1/ETH2/EPHY/ETH), a >> configurable divider (NSS/PPE/PON), or a rate-select bit (EPHY-RAW). >> This /2 stage is present in the CMN PLL block on every SoC supported >> by this driver, not just IPQ5210. >> >> Register this /2 stage once as a fixed-factor clock, "cmn_pll_div2", >> and store it on struct clk_cmn_pll so the output clock types added by >> later patches can parent on it. The two plain fixed-rate outputs, >> xo-24mhz and sleep-32khz, are the exception on IPQ5210 SoC: they stay >> parented directly on the main PLL clock. >> >> On SoCs other than IPQ5210, every output clock is a plain fixed-rate >> clock (CMN_PLL_CLK_FIXED_RATE) whose rate is a hardcoded absolute >> value rather than one computed from the parent rate, so this /2 clock >> is registered there but currently has no consumers; IPQ5210 is simply >> the first SoC in this driver whose output clocks are modeled as >> depending on parent_rate, which is what makes the /2 stage significant. >> >> This patch only registers the clock; later patches wire it in as the >> effective parent for the output clock types that sit downstream of it. > > Do not mention future patches here. Each patch has to stand by itself. > I will remove the reference to later patches and ensure that this patch is self-contained. >> >> Signed-off-by: Luo Jie >> --- >> drivers/clk/qcom/ipq-cmn-pll.c | 22 ++++++++++++++++++++++ >> 1 file changed, 22 insertions(+) >> >> diff --git a/drivers/clk/qcom/ipq-cmn-pll.c b/drivers/clk/qcom/ipq-cmn-pll.c >> index 4fdf78f6829e..bcb51a5f559a 100644 >> --- a/drivers/clk/qcom/ipq-cmn-pll.c >> +++ b/drivers/clk/qcom/ipq-cmn-pll.c >> @@ -96,10 +96,17 @@ struct cmn_pll_fixed_output_clk { >> * struct clk_cmn_pll - CMN PLL hardware specific data >> * @regmap: hardware regmap. >> * @hw: handle between common and hardware-specific interfaces >> + * @div2_hw: fixed /2 clock derived from the CMN PLL output; present on >> + * every supported SoC, but only IPQ5210 currently parents >> + * any output clock on it (every output clock except the >> + * plain fixed-rate xo/sleep clocks, which stay on the main >> + * PLL); other SoCs' output clocks use hardcoded rates that >> + * never depend on a parent >> */ >> struct clk_cmn_pll { >> struct regmap *regmap; >> struct clk_hw hw; >> + struct clk_hw *div2_hw; >> }; >> >> #define CLK_PLL_OUTPUT(_id, _name, _rate) { \ >> @@ -362,6 +369,7 @@ static int ipq_cmn_pll_register_clks(struct platform_device *pdev) >> const struct cmn_pll_fixed_output_clk *p, *fixed_clk; >> struct clk_hw_onecell_data *hw_data; >> struct device *dev = &pdev->dev; >> + struct clk_cmn_pll *cmn_pll; >> struct clk_hw *cmn_pll_hw; >> unsigned int num_clks; >> struct clk_hw *hw; >> @@ -388,6 +396,20 @@ static int ipq_cmn_pll_register_clks(struct platform_device *pdev) >> if (IS_ERR(cmn_pll_hw)) >> return PTR_ERR(cmn_pll_hw); >> >> + cmn_pll = to_clk_cmn_pll(cmn_pll_hw); >> + >> + /* >> + * The CMN PLL output feeds a shared, physical /2 stage ahead of >> + * any further per-clock processing (a gated fixed rate, a >> + * configurable divider, or a rate-select bit). Register it once >> + * as a fixed-factor clock so the output clock types added by >> + * later patches can parent on it. > > The comment here should only say why this is needed. Do not mention > future patches. > Understood, thanks. >> + */ >> + cmn_pll->div2_hw = devm_clk_hw_register_fixed_factor_parent_hw(dev, "cmn_pll_div2", >> + cmn_pll_hw, 0, 1, 2); >> + if (IS_ERR(cmn_pll->div2_hw)) >> + return PTR_ERR(cmn_pll->div2_hw); > > In fact, I think this clock registering is self explanatory as is, so you > should drop the comment above it. > Agreed. I will drop the comment above the clock registration. >> + >> /* Register the fixed rate output clocks. */ >> for (i = 0; i < num_clks; i++) { >> struct clk_parent_data pdata = { .hw = cmn_pll_hw }; >> >> -- >> 2.43.0 >>