[GIT PULL 5/5] soc: sophgo devicetree updates for 6.16

["Arnd Bergmann" <arnd@arndb.de>]

The following changes since commit a5806cd506af5a7c19bcd596e4708b5c464bfd21:

  Linux 6.15-rc7 (2025-05-18 13:57:29 -0700)

are available in the Git repository at:

  https://git.kernel.org/pub/scm/linux/kernel/git/soc/soc.git tags/soc-newsoc-6.16

for you to fetch changes up to 9bba618694cc905b898661c18e3e40955573ef5e:

  Merge tag 'riscv-sophgo-dt-for-v6.16' of https://github.com/sophgo/linux into soc/late (2025-05-23 23:59:45 +0200)

----------------------------------------------------------------
soc: sophgo devicetree updates for 6.16

The Sophgo SG2044 SoC is their second generation server chip
with 64 cores, following the SG2042.

In addition, there are minor updates for the cv180x SoCs.

----------------------------------------------------------------
Arnd Bergmann (1):
      Merge tag 'riscv-sophgo-dt-for-v6.16' of https://github.com/sophgo/linux into soc/late

Inochi Amaoto (10):
      riscv: dts: sophgo: sg2042: add pinctrl support
      riscv: dts: sophgo: Move all soc specific device into soc dtsi file
      riscv: dts: sophgo: Move riscv cpu definition to a separate file
      riscv: dts: sophgo: rename header file cv18xx.dtsi to cv180x.dtsi
      riscv: dts: sopgho: use SOC_PERIPHERAL_IRQ to calculate interrupt number
      dt-bindings: interrupt-controller: Add Sophgo SG2044 CLINT mswi
      dt-bindings: interrupt-controller: Add Sophgo SG2044 PLIC
      dt-bindings: riscv: sophgo: Add SG2044 compatible string
      riscv: dts: sophgo: Add initial device tree of Sophgo SRD3-10
      riscv: dts: sophgo: switch precise compatible for existed clock device for CV18XX

Zixian Zeng (1):
      riscv: sophgo: dts: Add spi controller for SG2042

 .../interrupt-controller/sifive,plic-1.0.0.yaml    |    1 +
 .../thead,c900-aclint-mswi.yaml                    |    1 +
 .../devicetree/bindings/riscv/sophgo.yaml          |    4 +
 arch/riscv/boot/dts/sophgo/Makefile                |    1 +
 arch/riscv/boot/dts/sophgo/cv1800b.dtsi            |   39 +-
 arch/riscv/boot/dts/sophgo/cv180x-cpus.dtsi        |   36 +
 .../boot/dts/sophgo/{cv18xx.dtsi => cv180x.dtsi}   |   95 +-
 arch/riscv/boot/dts/sophgo/cv1812h.dtsi            |   39 +-
 arch/riscv/boot/dts/sophgo/cv181x.dtsi             |    2 +-
 arch/riscv/boot/dts/sophgo/sg2002.dtsi             |   39 +-
 .../riscv/boot/dts/sophgo/sg2042-milkv-pioneer.dts |   72 +
 arch/riscv/boot/dts/sophgo/sg2042.dtsi             |   32 +
 arch/riscv/boot/dts/sophgo/sg2044-cpus.dtsi        | 3002 ++++++++++++++++++++
 arch/riscv/boot/dts/sophgo/sg2044-reset.h          |  128 +
 .../boot/dts/sophgo/sg2044-sophgo-srd3-10.dts      |   32 +
 arch/riscv/boot/dts/sophgo/sg2044.dtsi             |   86 +
 16 files changed, 3502 insertions(+), 107 deletions(-)
 create mode 100644 arch/riscv/boot/dts/sophgo/cv180x-cpus.dtsi
 rename arch/riscv/boot/dts/sophgo/{cv18xx.dtsi => cv180x.dtsi} (75%)
 create mode 100644 arch/riscv/boot/dts/sophgo/sg2044-cpus.dtsi
 create mode 100644 arch/riscv/boot/dts/sophgo/sg2044-reset.h
 create mode 100644 arch/riscv/boot/dts/sophgo/sg2044-sophgo-srd3-10.dts
 create mode 100644 arch/riscv/boot/dts/sophgo/sg2044.dtsi