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[103.229.16.4]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-8614f872269sm105836b3a.6.2026.09.03.08.36.02 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 03 Sep 2026 08:36:06 -0700 (PDT) Message-ID: Date: Thu, 3 Sep 2026 23:36:01 +0800 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v3 09/12] clk: qcom: ipq-cmn-pll: Add clock gate support for fixed clocks To: Konrad Dybcio , Bjorn Andersson , Michael Turquette , Stephen Boyd , Brian Masney , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Konrad Dybcio Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, quic_kkumarcs@quicinc.com, quic_linchen@quicinc.com, quic_leiwei@quicinc.com, quic_suruchia@quicinc.com References: <20260814-qcom_ipq5210_cmnpll-v3-0-21c3db378611@oss.qualcomm.com> <20260814-qcom_ipq5210_cmnpll-v3-9-21c3db378611@oss.qualcomm.com> Content-Language: en-US From: Jie Luo In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Proofpoint-GUID: Xc9zGs_vdkiMb1QGcfFHYP0Cf26LCz3q X-Authority-Analysis: v=2.4 cv=TqjWQjXh c=1 sm=1 tr=0 ts=6a9993ea cx=c_pps a=m5Vt/hrsBiPMCU0y4gIsQw==:117 a=nuhDOHQX5FNHPW3J6Bj6AA==:17 a=IkcTkHD0fZMA:10 a=VdqzKS8jKosA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=rJkE3RaqiGZ5pbrm-msn:22 a=QVThMpbGrsNalZwocfEA:9 a=QEXdDO2ut3YA:10 a=IoOABgeZipijB_acs4fv:22 X-Proofpoint-ORIG-GUID: Xc9zGs_vdkiMb1QGcfFHYP0Cf26LCz3q X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwOTAzMDEzNSBTYWx0ZWRfXz3dcA/8hwEim FtNLgejTnDJ1jaumZsxUcu7pUxhbLQfLKzm0/4N7YH8Fpj4DdNPCd8B7e5zDurs43oNT+WqqnaQ HBljYQjD5UdEz8JTYyygl+6TT8UIPurl7ItrGr8cuLKfGBmGXKSJQYKnvo6Uij0ueeJcGss97KE ktBeNI198g1ctrbcGP1Y4UijHDv1YjZ+iMcVrea7NYFA2VUEEN2F8knDGbxYvOvuEsBwRiRdW1e QaR5epvfKD5wZ6FxCbjVuVFCiIbVUPHEJGZllQJxOVPkh/tR+OqrZQIBQPZFCwLKbMT1fpdz8pj A6qvp61xEHqYquLUaNPu06Bpw7FkvRk1zW5CilWnsOAD4fzpAhECv4DHDMsscVXAtJlKXHLT2Qz 35I3GHTiUTcK53IlHQoDw0AByMRnK0s2jMISRJ5CAbQE1PtHrwAcBXZDIOWRz9xIYK0VfE0p/nD ZWJVQri63e2RyZczFUg== X-Proofpoint-Spam-Info: AW1haW4tMjYwOTAzMDEzNSBTYWx0ZWRfX3XiVg/RzdslB Dw5W6cLDfNHK6yPZE1JfuqYWUE+yYyG/tAW2zvU14gdOJl3i+teV+j1XcpQw2F3bh2eYewrFVXs Qqn+Fk03kvLQVDpm8wHzsDObTkOq+1E= X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-09-03_04,2026-09-03_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 phishscore=0 suspectscore=0 lowpriorityscore=0 adultscore=0 clxscore=1015 malwarescore=0 spamscore=0 priorityscore=1501 bulkscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2609030135 On 9/3/2026 7:59 PM, Konrad Dybcio wrote: > On 8/14/26 2:48 PM, Luo Jie wrote: >> Some CMN PLL output clocks require a hardware gate in addition to a >> fixed rate. The gate control bits reside in the register >> CMN_PLL_OUTPUT_RELATED_1 (0x79c). Each such clock is registered via a >> new struct clk_fixed_gate and clk_fixed_gate_ops, combining a fixed >> rate with enable/disable/is_enabled gate control through the shared >> regmap for CMN_PLL_OUTPUT_RELATED_1. > > [...] > >> +static int clk_fixed_gate_enable(struct clk_hw *hw) >> +{ >> + struct clk_fixed_gate *gate_clk = to_clk_fixed_gate(hw); >> + >> + return regmap_set_bits(gate_clk->regmap, CMN_PLL_OUTPUT_RELATED_1, >> + BIT(gate_clk->enable_bit)); >> +} >> + >> +static void clk_fixed_gate_disable(struct clk_hw *hw) >> +{ >> + struct clk_fixed_gate *gate_clk = to_clk_fixed_gate(hw); >> + >> + regmap_clear_bits(gate_clk->regmap, CMN_PLL_OUTPUT_RELATED_1, >> + BIT(gate_clk->enable_bit)); >> +} >> + >> +static int clk_fixed_gate_is_enabled(struct clk_hw *hw) >> +{ >> + struct clk_fixed_gate *gate_clk = to_clk_fixed_gate(hw); >> + >> + return regmap_test_bits(gate_clk->regmap, CMN_PLL_OUTPUT_RELATED_1, >> + BIT(gate_clk->enable_bit)); >> +} > > This is also all just clk_regmap / clk_branch > > Konrad OK. I will use the existing clk_regmap/clk_branch infrastructure for these gated outputs.