From: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
To: Wenbin Mei <wenbin.mei@mediatek.com>,
Ulf Hansson <ulf.hansson@linaro.org>
Cc: Chaotian Jing <chaotian.jing@mediatek.com>,
Matthias Brugger <matthias.bgg@gmail.com>,
Adrian Hunter <adrian.hunter@intel.com>,
Ritesh Harjani <riteshh@codeaurora.org>,
Asutosh Das <asutoshd@codeaurora.org>,
linux-mmc@vger.kernel.org, linux-kernel@vger.kernel.org,
linux-arm-kernel@lists.infradead.org,
linux-mediatek@lists.infradead.org
Subject: Re: [PATCH v4] mmc: mtk-sd: reduce CIT for better performance
Date: Tue, 6 Jun 2023 09:46:01 +0200 [thread overview]
Message-ID: <d9f506ff-d088-98d0-7f4b-d1f9db93d3e6@collabora.com> (raw)
In-Reply-To: <20230605121442.23622-1-wenbin.mei@mediatek.com>
Il 05/06/23 14:14, Wenbin Mei ha scritto:
> CQHCI_SSC1 indicates to CQE the polling period to use when using periodic
> SEND_QUEUE_STATUS(CMD13) polling.
> Since MSDC CQE uses msdc_hclk as ITCFVAL, so driver should use hclk
> frequency to get the actual time.
> The default value 0x1000 that corresponds to 150us for MediaTek SoCs, let's
> decrease it to 0x40 that corresponds to 2.35us, which can improve the
> performance of some eMMC devices.
>
> Signed-off-by: Wenbin Mei <wenbin.mei@mediatek.com>
> ---
> drivers/mmc/host/cqhci.h | 1 +
> drivers/mmc/host/mtk-sd.c | 45 +++++++++++++++++++++++++++++++++++++++
> 2 files changed, 46 insertions(+)
>
> diff --git a/drivers/mmc/host/cqhci.h b/drivers/mmc/host/cqhci.h
> index ba9387ed90eb..292b89ebd978 100644
> --- a/drivers/mmc/host/cqhci.h
> +++ b/drivers/mmc/host/cqhci.h
> @@ -23,6 +23,7 @@
> /* capabilities */
> #define CQHCI_CAP 0x04
> #define CQHCI_CAP_CS 0x10000000 /* Crypto Support */
> +#define CQHCI_CAP_ITCFMUL(x) (((x) & GENMASK(15, 12)) >> 12)
>
> /* configuration */
> #define CQHCI_CFG 0x08
> diff --git a/drivers/mmc/host/mtk-sd.c b/drivers/mmc/host/mtk-sd.c
> index edade0e54a0c..9f540973caff 100644
> --- a/drivers/mmc/host/mtk-sd.c
> +++ b/drivers/mmc/host/mtk-sd.c
> @@ -473,6 +473,7 @@ struct msdc_host {
> struct msdc_tune_para def_tune_para; /* default tune setting */
> struct msdc_tune_para saved_tune_para; /* tune result of CMD21/CMD19 */
> struct cqhci_host *cq_host;
> + u32 cq_ssc1_time;
> };
>
> static const struct mtk_mmc_compatible mt2701_compat = {
> @@ -2450,9 +2451,48 @@ static void msdc_hs400_enhanced_strobe(struct mmc_host *mmc,
> }
> }
>
> +static void msdc_cqe_cit_cal(struct msdc_host *host, u64 timer_ns)
> +{
> + struct mmc_host *mmc = mmc_from_priv(host);
> + struct cqhci_host *cq_host = mmc->cqe_private;
> + u8 itcfmul;
> + u64 hclk_freq;
> + u64 value;
> +
> + /* Since MSDC CQE uses msdc_hclk as ITCFVAL, so driver should use hclk
> + * frequency to get the actual time for CIT.
> + */
/*
* On MediaTek SoCs the MSDC controller's CQE uses msdc_hclk as ITCFVAL
* so we multiply/divide the HCLK frequency by ITCFMUL to calculate the
* Send Status Command Idle Timer (CIT) value.
*/
The proposed comment increases readability.
Cheers,
Angelo
next prev parent reply other threads:[~2023-06-06 7:51 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-06-05 12:14 Wenbin Mei
2023-06-05 13:22 ` AngeloGioacchino Del Regno
2023-06-06 1:26 ` Wenbin Mei (梅文彬)
2023-06-05 13:46 ` Alexandre Mergnat
2023-06-06 1:33 ` Wenbin Mei (梅文彬)
2023-06-06 7:46 ` AngeloGioacchino Del Regno [this message]
2023-06-06 7:57 ` Wenbin Mei (梅文彬)
2023-06-06 8:58 ` Adrian Hunter
2023-06-06 11:03 ` Wenbin Mei (梅文彬)
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