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unknown-38-66.xilinx.com ([149.199.38.66] helo=xsj-pvapsmtp01) by xsj-pvapsmtpgw01 with esmtp (Exim 4.63) (envelope-from ) id 1fxptE-0003tB-NB; Thu, 06 Sep 2018 01:43:48 -0700 Received: from [127.0.0.1] (helo=localhost) by xsj-pvapsmtp01 with smtp (Exim 4.63) (envelope-from ) id 1fxpt9-00033z-Jp; Thu, 06 Sep 2018 01:43:43 -0700 Received: from [172.30.17.111] by xsj-pvapsmtp01 with esmtp (Exim 4.63) (envelope-from ) id 1fxpt5-0002z7-72; Thu, 06 Sep 2018 01:43:39 -0700 Subject: Re: [PATCH 1/1] axi-i2s: set period size register To: Luca Ceresoli , Lars-Peter Clausen , CC: Liam Girdwood , Mark Brown , Jaroslav Kysela , Takashi Iwai , , Michal Simek References: <20180824160430.10222-1-luca@lucaceresoli.net> <20180824160430.10222-2-luca@lucaceresoli.net> <263e42b4-75a3-183c-894b-e485e387eccf@lucaceresoli.net> From: Michal Simek Message-ID: Date: Thu, 6 Sep 2018 10:43:36 +0200 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101 Thunderbird/52.9.1 MIME-Version: 1.0 In-Reply-To: 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xilinx.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 06 Sep 2018 08:43:49.1633 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 3d82048a-5ea0-49a5-c52e-08d613d4dde5 X-MS-Exchange-CrossTenant-Id: 657af505-d5df-48d0-8300-c31994686c5c X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=657af505-d5df-48d0-8300-c31994686c5c;Ip=[149.199.60.83];Helo=[xsj-pvapsmtpgw01] X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM2PR02MB510 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 27.8.2018 18:22, Luca Ceresoli wrote: > Hi, > > thanks for your feedback. > > [Adding Michal Simek (Xilinx maintainer) in Cc] > > On 27/08/2018 14:27, Lars-Peter Clausen wrote: >> On 08/24/2018 06:04 PM, Luca Ceresoli wrote: >>> The default value of the PERIOD_LEN register is 0 and results in >>> axi-i2s keeping TLAST always asserted in its AXI Stream output. >>> >>> When the AXI Stream is sent to a Xilinx AXI-DMA, this results in the >>> DMA generating an interrupt flood and ALSA produce a corrupted >>> recording. This is because AXI-DMA raises an interrupt whenever TLAST >>> is active. >>> >>> Fix by setting the PERIOD_LEN register as soon as the period is >>> known. This way TLAST is emitted once per period, and the DMA raises >>> interrupts correctly. >> >> The patch looks OK. But I'd prefer not to merge it if possible. >> >> We've done some early experiments with the Xilinx AXI-DMA, but it turned out >> to be to unreliable and we've abandoned support for it. One of the more >> critical issues was that you can't abort a DMA transfer. That means when >> audio capture is stopped the DMA will halt, but not complete the current >> transfer. Then when the next audio capture start the DMA will continue with >> the previous transfer. The observed effect of this was that the system would >> just crash randomly (Presumably due to memory corruption). > > Strange. I have done many capture experiments with arecord and didn't > run into such bad issues. I only have a much less serious problem > (garbage or old samples in the first few buffers), but no crashes. > > Michal, are you aware of these problems? I have never played with i2c and axi dma. We wanted to use this solution for ultra96 but we didn't finish it. Also there is new i2s IP which is going to xilinx tree and it is more recent but also I didn't test it but at least IP team/sw guys can look at issues with it. Thanks, Michal