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([2001:b07:6468:f312:5e2c:eb9a:a8b6:fd3e]) by smtp.gmail.com with ESMTPSA id q17sm10126364edd.57.2021.10.06.04.23.40 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 06 Oct 2021 04:23:43 -0700 (PDT) Message-ID: Date: Wed, 6 Oct 2021 13:23:39 +0200 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:91.0) Gecko/20100101 Thunderbird/91.1.0 Subject: Re: [PATCH MANUALSEL 5.4 3/4] kvm: x86: Add AMD PMU MSRs to msrs_to_save_all[] Content-Language: en-US To: Sasha Levin , linux-kernel@vger.kernel.org, stable@vger.kernel.org Cc: Fares Mehanna , tglx@linutronix.de, mingo@redhat.com, bp@alien8.de, x86@kernel.org, kvm@vger.kernel.org References: <20211006111250.264294-1-sashal@kernel.org> <20211006111250.264294-3-sashal@kernel.org> From: Paolo Bonzini In-Reply-To: <20211006111250.264294-3-sashal@kernel.org> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 06/10/21 13:12, Sasha Levin wrote: > From: Fares Mehanna > > [ Upstream commit e1fc1553cd78292ab3521c94c9dd6e3e70e606a1 ] > > Intel PMU MSRs is in msrs_to_save_all[], so add AMD PMU MSRs to have a > consistent behavior between Intel and AMD when using KVM_GET_MSRS, > KVM_SET_MSRS or KVM_GET_MSR_INDEX_LIST. > > We have to add legacy and new MSRs to handle guests running without > X86_FEATURE_PERFCTR_CORE. > > Signed-off-by: Fares Mehanna > Message-Id: <20210915133951.22389-1-faresx@amazon.de> > Signed-off-by: Paolo Bonzini > Signed-off-by: Sasha Levin > --- > arch/x86/kvm/x86.c | 7 +++++++ > 1 file changed, 7 insertions(+) > > diff --git a/arch/x86/kvm/x86.c b/arch/x86/kvm/x86.c > index 69e286edb2c9..4948bf36bd0a 100644 > --- a/arch/x86/kvm/x86.c > +++ b/arch/x86/kvm/x86.c > @@ -1239,6 +1239,13 @@ static const u32 msrs_to_save_all[] = { > MSR_ARCH_PERFMON_EVENTSEL0 + 12, MSR_ARCH_PERFMON_EVENTSEL0 + 13, > MSR_ARCH_PERFMON_EVENTSEL0 + 14, MSR_ARCH_PERFMON_EVENTSEL0 + 15, > MSR_ARCH_PERFMON_EVENTSEL0 + 16, MSR_ARCH_PERFMON_EVENTSEL0 + 17, > + > + MSR_K7_EVNTSEL0, MSR_K7_EVNTSEL1, MSR_K7_EVNTSEL2, MSR_K7_EVNTSEL3, > + MSR_K7_PERFCTR0, MSR_K7_PERFCTR1, MSR_K7_PERFCTR2, MSR_K7_PERFCTR3, > + MSR_F15H_PERF_CTL0, MSR_F15H_PERF_CTL1, MSR_F15H_PERF_CTL2, > + MSR_F15H_PERF_CTL3, MSR_F15H_PERF_CTL4, MSR_F15H_PERF_CTL5, > + MSR_F15H_PERF_CTR0, MSR_F15H_PERF_CTR1, MSR_F15H_PERF_CTR2, > + MSR_F15H_PERF_CTR3, MSR_F15H_PERF_CTR4, MSR_F15H_PERF_CTR5, > }; > > static u32 msrs_to_save[ARRAY_SIZE(msrs_to_save_all)]; > Acked-by: Paolo Bonzini