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AJvYcCWmHO5xl9JEyiaXwHn34l19wM0FxdmK8M83v6VBhxjnwlVnQMNlCkx0qMOa4RpictR7/HJO8/2ZAdN9WKO0D1HQ5W8CuDtkomnJtPfq X-Gm-Message-State: AOJu0YyZL9uwnAAjEKjmcWZTstoQMeAYfjVqzR//230hEM5uG7Cmon7V Lelkj76QBDYAeBJve3fZYm3lokbMnzvOc6YRVw3WhLTUslyvgpgAYXb+ZDEzq4Q= X-Google-Smtp-Source: AGHT+IF5soNWoBfxIJAzPM7ulE2ztXx3R64HiLhLbDOWs9lCmTj3XqnA7S+bNE2jbslzIWMskkLVPA== X-Received: by 2002:a05:6e02:b2d:b0:396:4314:2bcf with SMTP id e9e14a558f8ab-39643142de5mr67747935ab.19.1721350394158; Thu, 18 Jul 2024 17:53:14 -0700 (PDT) Received: from [100.64.0.1] ([147.124.94.167]) by smtp.gmail.com with ESMTPSA id e9e14a558f8ab-397f60fc088sm897415ab.50.2024.07.18.17.53.12 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 18 Jul 2024 17:53:13 -0700 (PDT) Message-ID: Date: Thu, 18 Jul 2024 19:53:11 -0500 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v3 09/11] riscv: Add ISA extension parsing for Ziccrse To: Alexandre Ghiti References: <20240717061957.140712-1-alexghiti@rivosinc.com> <20240717061957.140712-10-alexghiti@rivosinc.com> Content-Language: en-US From: Samuel Holland Cc: Jonathan Corbet , Paul Walmsley , Palmer Dabbelt , Albert Ou , Conor Dooley , Rob Herring , Krzysztof Kozlowski , Andrea Parri , Nathan Chancellor , Peter Zijlstra , Ingo Molnar , Will Deacon , Waiman Long , Boqun Feng , Arnd Bergmann , Leonardo Bras , Guo Ren , linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, linux-arch@vger.kernel.org In-Reply-To: <20240717061957.140712-10-alexghiti@rivosinc.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit Hi Alex, On 2024-07-17 1:19 AM, Alexandre Ghiti wrote: > Add support to parse the Ziccrse string in the riscv,isa string. > > Signed-off-by: Alexandre Ghiti > --- > arch/riscv/include/asm/hwcap.h | 1 + > arch/riscv/kernel/cpufeature.c | 1 + > 2 files changed, 2 insertions(+) > > diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h > index f71ddd2ca163..863b9b7d4a4f 100644 > --- a/arch/riscv/include/asm/hwcap.h > +++ b/arch/riscv/include/asm/hwcap.h > @@ -82,6 +82,7 @@ > #define RISCV_ISA_EXT_ZACAS 73 > #define RISCV_ISA_EXT_XANDESPMU 74 > #define RISCV_ISA_EXT_ZABHA 75 > +#define RISCV_ISA_EXT_ZICCRSE 76 > > #define RISCV_ISA_EXT_XLINUXENVCFG 127 > > diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c > index c125d82c894b..93d8cc7e232c 100644 > --- a/arch/riscv/kernel/cpufeature.c > +++ b/arch/riscv/kernel/cpufeature.c > @@ -306,6 +306,7 @@ const struct riscv_isa_ext_data riscv_isa_ext[] = { > __RISCV_ISA_EXT_DATA(svnapot, RISCV_ISA_EXT_SVNAPOT), > __RISCV_ISA_EXT_DATA(svpbmt, RISCV_ISA_EXT_SVPBMT), > __RISCV_ISA_EXT_DATA(xandespmu, RISCV_ISA_EXT_XANDESPMU), > + __RISCV_ISA_EXT_DATA(ziccrse, RISCV_ISA_EXT_ZICCRSE), Please sort this entry per the comment at the beginning of the array. Regards, Samuel > }; > > const size_t riscv_isa_ext_count = ARRAY_SIZE(riscv_isa_ext);