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Tue, 04 Feb 2025 17:33:49 +0000 (GMT) Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA01.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 514HXmKl001124 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 4 Feb 2025 17:33:48 GMT Received: from [10.216.62.245] (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Tue, 4 Feb 2025 09:33:44 -0800 Message-ID: Date: Tue, 4 Feb 2025 23:03:41 +0530 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2 1/2] arm64: dts: qcom: qcs615: Add clock nodes for multimedia clock To: Konrad Dybcio , Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley CC: Ajit Pandey , Imran Shaik , Jagadeesh Kona , , , References: <20250119-qcs615-mm-v2-dt-nodes-v2-0-c46ab4080989@quicinc.com> <20250119-qcs615-mm-v2-dt-nodes-v2-1-c46ab4080989@quicinc.com> <19a83d67-7e1a-495b-8dff-e1d2ba05b878@oss.qualcomm.com> Content-Language: en-US From: Taniya Das In-Reply-To: <19a83d67-7e1a-495b-8dff-e1d2ba05b878@oss.qualcomm.com> Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 7bit X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: c4JAX9SwW01lt6SO9zeJVRQ6s4YQFfdn X-Proofpoint-ORIG-GUID: c4JAX9SwW01lt6SO9zeJVRQ6s4YQFfdn X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1057,Hydra:6.0.680,FMLib:17.12.68.34 definitions=2025-02-04_08,2025-02-04_01,2024-11-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 mlxscore=0 malwarescore=0 lowpriorityscore=0 adultscore=0 impostorscore=0 mlxlogscore=999 spamscore=0 phishscore=0 clxscore=1015 bulkscore=0 suspectscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2501170000 definitions=main-2502040135 On 2/3/2025 7:44 PM, Konrad Dybcio wrote: > On 19.01.2025 1:00 PM, Taniya Das wrote: >> Add support for video, camera, display and gpu clock controller nodes >> for QCS615 platform. >> >> Signed-off-by: Taniya Das >> --- >> arch/arm64/boot/dts/qcom/qcs615.dtsi | 51 ++++++++++++++++++++++++++++++++++++ >> 1 file changed, 51 insertions(+) >> >> diff --git a/arch/arm64/boot/dts/qcom/qcs615.dtsi b/arch/arm64/boot/dts/qcom/qcs615.dtsi >> index f4abfad474ea62dea13d05eb874530947e1e8d3e..9d537019437c5202c4d398eecd0ce2a991083175 100644 >> --- a/arch/arm64/boot/dts/qcom/qcs615.dtsi >> +++ b/arch/arm64/boot/dts/qcom/qcs615.dtsi >> @@ -3,7 +3,11 @@ >> * Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserved. >> */ >> >> +#include >> +#include >> #include >> +#include >> +#include >> #include >> #include >> #include >> @@ -1418,6 +1422,18 @@ data-pins { >> }; >> }; >> >> + gpucc: clock-controller@5090000 { >> + compatible = "qcom,qcs615-gpucc"; >> + reg = <0 0x05090000 0 0x9000>; >> + >> + clocks = <&rpmhcc RPMH_CXO_CLK>, >> + <&gcc GPLL0>; > > This would normally be GCC_GPU_GPLL0_(DIV_)CLK_SRC, is this intentional? > Yes, Konard, but on QCS615 GPLL0 is connected and not the GCC_GPU_GPLL0 sources. > Konrad -- Thanks & Regards, Taniya Das.