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[78.88.45.245]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-aff08b86833sm2622560666b.48.2025.09.09.04.21.20 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 09 Sep 2025 04:21:21 -0700 (PDT) Message-ID: Date: Tue, 9 Sep 2025 13:21:19 +0200 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v3 3/5] dt-bindings: phy: qcom,sc8280xp-qmp-usb43dp-phy: Document lanes mapping when not using in USB-C complex To: Dmitry Baryshkov , Neil Armstrong Cc: Andrzej Hajda , Robert Foss , Laurent Pinchart , Jonas Karlman , Jernej Skrabec , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Vinod Koul , Kishon Vijay Abraham I , Bjorn Andersson , Konrad Dybcio , dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org References: <20250908-topic-x1e80100-hdmi-v3-0-c53b0f2bc2fb@linaro.org> <20250908-topic-x1e80100-hdmi-v3-3-c53b0f2bc2fb@linaro.org> <7dzfcuvr45h4iailtjutqjev7lofoqu7w6ob77gehgmy7mctpk@k7oob4wj3c7a> <14d58c6d-ca20-4349-8031-9906a4539fef@linaro.org> Content-Language: en-US From: Konrad Dybcio In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Proofpoint-ORIG-GUID: rztAI6jR90raPRLPXZeK0hmHE5Bcnx_5 X-Proofpoint-GUID: rztAI6jR90raPRLPXZeK0hmHE5Bcnx_5 X-Authority-Analysis: v=2.4 cv=NdLm13D4 c=1 sm=1 tr=0 ts=68c00db4 cx=c_pps a=EVbN6Ke/fEF3bsl7X48z0g==:117 a=FpWmc02/iXfjRdCD7H54yg==:17 a=IkcTkHD0fZMA:10 a=yJojWOMRYYMA:10 a=KKAkSRfTAAAA:8 a=iAPsCBKfci-S516yzPgA:9 a=QEXdDO2ut3YA:10 a=a_PwQJl-kcHnX1M80qC6:22 a=cvBusfyB2V15izCimMoJ:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwOTA4MDA2NiBTYWx0ZWRfX/prljYoDalio oDNjAlhcIfJAL1FCk1xO22o/tLfw14jfSfgNrSvKrAZIxE5Cm46PueTz5Ct0cPx996zxeOIEp2e yiD9ucxvdL/S2khqljksmkwGK3cgRGkFNwfMC/+2EUYqBYaedje3mn8E85mi9mDzKI6Qnc/pbmX GTVZwPNa1FIU7Gt75DyJiQGvwe7H2iDbdkoToaTmQOmkolRBmPcPJYY8+mS/X87PlhnWpYc/zbY xNgHz/NBGTEf7YauPZ10R1nZjEz3FVAAeJuboDvHuQDvRsNKRA+wEgOGky+Rp7bZG3G3N+CH3zt HsPy2n8fAiZKvJzNqvl3SYvVi60JTIWolLl89NNJ2cnqZCCDDBT1pW24S9faipn0klrRbkGBZ6+ AVXRfOaK X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1117,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-09-09_01,2025-09-08_02,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 bulkscore=0 adultscore=0 suspectscore=0 phishscore=0 clxscore=1015 impostorscore=0 spamscore=0 priorityscore=1501 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2507300000 definitions=main-2509080066 On 9/9/25 1:16 PM, Dmitry Baryshkov wrote: > On Tue, Sep 09, 2025 at 09:14:49AM +0200, Neil Armstrong wrote: >> On 08/09/2025 23:14, Dmitry Baryshkov wrote: >>> On Mon, Sep 08, 2025 at 03:04:20PM +0200, Neil Armstrong wrote: >>>> The QMP USB3/DP Combo PHY hosts an USB3 phy and a DP PHY on top >>>> of a combo glue to route either lanes to the 4 shared physical lanes. >>>> >>>> The routing of the lanes can be: >>>> - 2 DP + 2 USB3 >>>> - 4 DP >>>> - 2 USB3 >>>> >>>> The layout of the lanes was designed to be mapped and swapped >>>> related to the USB-C Power Delivery negociation, so it supports >>>> a finite set of mappings inherited by the USB-C Altmode layouts. >>>> >>>> Nevertheless those QMP Comby PHY can be used to drive a DisplayPort >>>> connector, DP->HDMI bridge, USB3 A Connector, etc... without >>>> an USB-C connector and no PD events. >>>> >>>> Document the data-lanes on numbered port@0 out endpoints, >>>> allowing us to document the lanes mapping to DisplayPort >>>> and/or USB3 connectors/peripherals. >>>> >>>> Signed-off-by: Neil Armstrong >>>> --- >>>> .../phy/qcom,sc8280xp-qmp-usb43dp-phy.yaml | 59 +++++++++++++++++++++- >>>> 1 file changed, 58 insertions(+), 1 deletion(-) >>>> >>>> diff --git a/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-usb43dp-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-usb43dp-phy.yaml >>>> index 5005514d7c3a1e4a8893883497fd204bc04e12be..51e0d0983091af0b8a5170ac34a05ab0acc435a3 100644 >>>> --- a/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-usb43dp-phy.yaml >>>> +++ b/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-usb43dp-phy.yaml >>>> @@ -81,10 +81,67 @@ properties: >>>> ports: >>>> $ref: /schemas/graph.yaml#/properties/ports >>>> + >>>> properties: >>>> port@0: >>>> - $ref: /schemas/graph.yaml#/properties/port >>>> + $ref: /schemas/graph.yaml#/$defs/port-base >>>> description: Output endpoint of the PHY >>>> + unevaluatedProperties: false >>>> + >>>> + properties: >>>> + endpoint: >>>> + $ref: /schemas/graph.yaml#/$defs/endpoint-base >>>> + unevaluatedProperties: false >>>> + >>>> + endpoint@0: >>>> + $ref: /schemas/graph.yaml#/$defs/endpoint-base >>>> + description: Display Port Output lanes of the PHY when used with static mapping >>>> + unevaluatedProperties: false >>>> + >>>> + properties: >>>> + data-lanes: >>>> + $ref: /schemas/types.yaml#/definitions/uint32-array >>>> + minItems: 2 >>> >>> Nit: DP can work in a 1-lane mode. Do we nned to support that in the PHY? >> >> So the PHY already supports 1-lane, but the QMP Combo only supports >> mapping 2+2 or 4, but nevetheless we can still decscribe 1 lane in DT >> int both in & out endpoint and still should work fine. >> >> Do you think this should be done now ? > > Do we support it in the PHY hardware? I don't think the PHY cares if it's 1 or 2 lanes Konrad