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Thu, 7 Aug 2025 17:29:25 -0500 Received: from DFLE101.ent.ti.com (10.64.6.22) by DFLE114.ent.ti.com (10.64.6.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.55; Thu, 7 Aug 2025 17:29:24 -0500 Received: from lelvem-mr06.itg.ti.com (10.180.75.8) by DFLE101.ent.ti.com (10.64.6.22) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.55 via Frontend Transport; Thu, 7 Aug 2025 17:29:24 -0500 Received: from [128.247.81.105] (judy-hp.dhcp.ti.com [128.247.81.105]) by lelvem-mr06.itg.ti.com (8.18.1/8.18.1) with ESMTP id 577MTOBE1764481; Thu, 7 Aug 2025 17:29:24 -0500 Message-ID: Date: Thu, 7 Aug 2025 17:29:24 -0500 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 2/4] soc: ti: k3-socinfo: Add support for AM62P variants To: Andrew Davis , Nishanth Menon , Tero Kristo , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Adrian Hunter , Ulf Hansson CC: Vignesh Raghavendra , Santosh Shilimkar , , , , References: <20250805234950.3781367-1-jm@ti.com> <20250805234950.3781367-3-jm@ti.com> <37f73812-be0c-43b2-a5bc-a41e09db85ea@ti.com> Content-Language: en-US From: Judith Mendez In-Reply-To: <37f73812-be0c-43b2-a5bc-a41e09db85ea@ti.com> Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 8bit X-C2ProcessedOrg: 333ef613-75bf-4e12-a4b1-8e3623f5dcea Hi Andrew, On 8/7/25 12:24 PM, Andrew Davis wrote: > On 8/5/25 6:49 PM, Judith Mendez wrote: >> This adds a support for detecting AM62P SR1.0, SR1.1, SR1.2. >> >> On AM62P, silicon revision is discovered with GP_SW1 instead of JTAGID >> register, so introduce GP_SW register range to determine SoC revision. >> >> Signed-off-by: Judith Mendez >> --- >>   drivers/soc/ti/k3-socinfo.c | 82 +++++++++++++++++++++++++++++++++---- >>   1 file changed, 74 insertions(+), 8 deletions(-) >> >> diff --git a/drivers/soc/ti/k3-socinfo.c b/drivers/soc/ti/k3-socinfo.c >> index d716be113c84..9daeced656d6 100644 >> --- a/drivers/soc/ti/k3-socinfo.c >> +++ b/drivers/soc/ti/k3-socinfo.c >> @@ -15,6 +15,7 @@ >>   #include >>   #define CTRLMMR_WKUP_JTAGID_REG        0 >> +#define CTRLMMR_WKUP_GP_SW1_REG        4 >>   /* >>    * Bits: >>    *  31-28 VARIANT    Device variant >> @@ -62,10 +63,63 @@ static const struct k3_soc_id { >>       { JTAG_ID_PARTNO_AM62LX, "AM62LX" }, >>   }; >> +static const struct regmap_config k3_chipinfo_regmap_cfg = { >> +    .reg_bits = 32, >> +    .val_bits = 32, >> +    .reg_stride = 4, >> +}; >> + >>   static const char * const j721e_rev_string_map[] = { >>       "1.0", "1.1", "2.0", >>   }; >> +static const char * const am62p_gpsw_rev_string_map[] = { >> +    "1.0", "1.1", "1.2", >> +}; >> + >> +static int >> +k3_chipinfo_get_variant_alternate(struct platform_device *pdev, >> unsigned int partno, u32 *variant) >> +{ >> +    struct device *dev = &pdev->dev; >> +    struct regmap *regmap; >> +    void __iomem *base; >> +    u32 offset; >> +    int ret; >> + >> +    base = devm_platform_ioremap_resource(pdev, 1); >> +    if (IS_ERR(base)) >> +        return PTR_ERR(base); >> + >> +    regmap = regmap_init_mmio(dev, base, &k3_chipinfo_regmap_cfg); > > devm_regmap_init_mmio() > > Otherwise this regmap never gets freed up in the error paths. Thanks for reviewing, but.... I have completely changed this patch in v2, feel free to review v2 though (: ..