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[78.88.45.245]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-b72d3baf872sm1427413366b.27.2025.11.12.02.07.44 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 12 Nov 2025 02:07:47 -0800 (PST) Message-ID: Date: Wed, 12 Nov 2025 11:07:43 +0100 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2 01/21] drm/msm/a6xx: Flush LRZ cache before PT switch To: Akhil P Oommen , Rob Clark , Bjorn Andersson , Konrad Dybcio , Sean Paul , Dmitry Baryshkov , Abhinav Kumar , Jessica Zhang , Marijn Suijten , David Airlie , Simona Vetter , Jonathan Marek , Jordan Crouse , Will Deacon , Robin Murphy , Joerg Roedel , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Connor Abbott Cc: linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-arm-kernel@lists.infradead.org, iommu@lists.linux.dev, devicetree@vger.kernel.org References: <20251110-kaana-gpu-support-v2-0-bef18acd5e94@oss.qualcomm.com> <20251110-kaana-gpu-support-v2-1-bef18acd5e94@oss.qualcomm.com> Content-Language: en-US From: Konrad Dybcio In-Reply-To: <20251110-kaana-gpu-support-v2-1-bef18acd5e94@oss.qualcomm.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUxMTEyMDA4MSBTYWx0ZWRfX8xuU4XKHFfGR iG568skmnO99cATt3eXugJ8i1wA3U9JyAp2LlVa52/uIUtoO27vRw+IvjXLIVs+gCl1PNXi/U9l PltFYbw54yyUz/tLgTmF2Kpt+mPKGaOdtHUX3qhYb7wwtua/Sjrlnp0OvU7SQhzvgA3n8ZBImvZ gUajt7JCE3lIXit3uGIfnLJxTY4/p6oa72IWyUf/W4o0Mh+i4JbKlGEtRb62M1VKt4mbFouoJF9 WCHzLEm9bsts4PuR6gEHUMmvif3lAt1RWr1lS8SbhXNpF1138PHkGXMpJP1gOmdXRqpU9blosMw dmrguH9QKSFG/LFPv4Gf74hsbVpa2dnynhu7DkGY2iY3VY5L8qxJGBl+URplzO39ZkC1q4X9+Vm V/zd1lLwY3199Nko6CXI5zXxI3YFDQ== X-Proofpoint-GUID: zCyxAXdwQBTe4XePYDEXb_Gje0SAsX1B X-Authority-Analysis: v=2.4 cv=bbBmkePB c=1 sm=1 tr=0 ts=69145c75 cx=c_pps a=JbAStetqSzwMeJznSMzCyw==:117 a=FpWmc02/iXfjRdCD7H54yg==:17 a=IkcTkHD0fZMA:10 a=6UeiqGixMTsA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=EUspDBNiAAAA:8 a=FVkm2KtGXHSZZ5XTrLgA:9 a=QEXdDO2ut3YA:10 a=uxP6HrT_eTzRwkO_Te1X:22 X-Proofpoint-ORIG-GUID: zCyxAXdwQBTe4XePYDEXb_Gje0SAsX1B X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.9,FMLib:17.12.100.49 definitions=2025-11-12_03,2025-11-11_03,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0 bulkscore=0 impostorscore=0 lowpriorityscore=0 priorityscore=1501 malwarescore=0 phishscore=0 spamscore=0 clxscore=1015 adultscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2510240001 definitions=main-2511120081 On 11/10/25 5:37 PM, Akhil P Oommen wrote: > As per the recommendation, A7x and newer GPUs should flush the LRZ cache > before switching the pagetable. Update a6xx_set_pagetable() to do this. > While we are at it, sync both BV and BR before issuing a > CP_RESET_CONTEXT_STATE command, to match the downstream sequence. > > Fixes: af66706accdf ("drm/msm/a6xx: Add skeleton A7xx support") > Signed-off-by: Akhil P Oommen > --- > drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 10 ++++++++-- > 1 file changed, 8 insertions(+), 2 deletions(-) > > diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c > index b8f8ae940b55..6f7ed07670b1 100644 > --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c > +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c > @@ -224,7 +224,7 @@ static void a6xx_set_pagetable(struct a6xx_gpu *a6xx_gpu, > OUT_RING(ring, submit->seqno - 1); > > OUT_PKT7(ring, CP_THREAD_CONTROL, 1); > - OUT_RING(ring, CP_SET_THREAD_BOTH); > + OUT_RING(ring, CP_THREAD_CONTROL_0_SYNC_THREADS | CP_SET_THREAD_BOTH); > > /* Reset state used to synchronize BR and BV */ > OUT_PKT7(ring, CP_RESET_CONTEXT_STATE, 1); > @@ -235,7 +235,13 @@ static void a6xx_set_pagetable(struct a6xx_gpu *a6xx_gpu, > CP_RESET_CONTEXT_STATE_0_RESET_GLOBAL_LOCAL_TS); > > OUT_PKT7(ring, CP_THREAD_CONTROL, 1); > - OUT_RING(ring, CP_SET_THREAD_BR); > + OUT_RING(ring, CP_THREAD_CONTROL_0_SYNC_THREADS | CP_SET_THREAD_BOTH); IIUC downstream doesn't sync here since there's a sync after the LRZ flush, but I don't think that's a meaningful difference. Reviewed-by: Konrad Dybcio Konrad