Re: [PATCH 07/12] KVM: SVM: Adding support for configuring x2APIC MSRs interception

[Suravee Suthikulpanit <suravee.suthikulpanit@amd.com>]

On 4/6/22 6:08 AM, Suravee Suthikulpanit wrote:
> diff --git a/arch/x86/kvm/svm/svm.c b/arch/x86/kvm/svm/svm.c
> index bbdc16c4b6d7..56ad9ba05111 100644
> --- a/arch/x86/kvm/svm/svm.c
> +++ b/arch/x86/kvm/svm/svm.c
> @@ -89,7 +89,7 @@ static uint64_t osvw_len = 4, osvw_status;
>   static DEFINE_PER_CPU(u64, current_tsc_ratio);
>   #define TSC_RATIO_DEFAULT	0x0100000000ULL
>   
> -static const struct svm_direct_access_msrs {
> +static struct svm_direct_access_msrs {
>   	u32 index;   /* Index of the MSR */
>   	bool always; /* True if intercept is initially cleared */
>   } direct_access_msrs[MAX_DIRECT_ACCESS_MSRS] = {
> @@ -786,6 +786,33 @@ static void add_msr_offset(u32 offset)
>   	BUG();
>   }
>   
> +static void init_direct_access_msrs(void)
> +{
> +	int i, j;
> +
> +	/* Find first MSR_INVALID */
> +	for (i = 0; i < MAX_DIRECT_ACCESS_MSRS; i++) {
> +		if (direct_access_msrs[i].index == MSR_INVALID)
> +			break;
> +	}
> +	BUG_ON(i >= MAX_DIRECT_ACCESS_MSRS);
> +
> +	/*
> +	 * Initialize direct_access_msrs entries to intercept X2APIC MSRs
> +	 * (range 0x800 to 0x8ff)
> +	 */
> +	for (j = 0; j < 0x100; j++) {
> +		direct_access_msrs[i + j].index = boot_cpu_has(X86_FEATURE_X2AVIC) ?
> +						  (APIC_BASE_MSR + j) : MSR_INVALID;

I found a bug in this part, when testing on system w/o support for x2AVIC feature.

The following change fixes the issue.

-               direct_access_msrs[i + j].index = boot_cpu_has(X86_FEATURE_X2AVIC) ?
-                                                 (APIC_BASE_MSR + j) : MSR_INVALID;
+               direct_access_msrs[i + j].index = (APIC_BASE_MSR + j);

I will update this in V2.

Regards,
Suravee