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Tue, 15 Feb 2022 17:49:57 +0100 (CET) Received: from Webmail-eu.st.com (sfhdag2node2.st.com [10.75.127.5]) by euls16034.sgp.st.com (STMicroelectronics) with ESMTP id 9117722FA24; Tue, 15 Feb 2022 17:49:57 +0100 (CET) Received: from [10.201.21.201] (10.75.127.49) by SFHDAG2NODE2.st.com (10.75.127.5) with Microsoft SMTP Server (TLS) id 15.0.1497.26; Tue, 15 Feb 2022 17:49:57 +0100 Message-ID: Date: Tue, 15 Feb 2022 17:49:56 +0100 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:91.0) Gecko/20100101 Thunderbird/91.5.0 Subject: Re: [PATCH v2 1/7] ARM: dts: sti: ensure unique unit-address in stih407-clock Content-Language: en-US To: Alain Volmat , Rob Herring CC: Arnd Bergmann , , , References: <20220211181614.683497-1-avolmat@me.com> <20220211181614.683497-2-avolmat@me.com> From: Patrice CHOTARD In-Reply-To: <20220211181614.683497-2-avolmat@me.com> Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: 7bit X-Originating-IP: [10.75.127.49] X-ClientProxiedBy: SFHDAG2NODE1.st.com (10.75.127.4) To SFHDAG2NODE2.st.com (10.75.127.5) X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.816,Hydra:6.0.425,FMLib:17.11.62.513 definitions=2022-02-15_04,2022-02-14_04,2021-12-02_01 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi ALain On 2/11/22 19:16, Alain Volmat wrote: > Move quadfs and a9-mux clocks nodes into clockgen nodes so > that they can get the reg property from the parent node and > ensure only one node has the address. > > Signed-off-by: Alain Volmat > --- > arch/arm/boot/dts/stih407-clock.dtsi | 101 ++++++++++++--------------- > 1 file changed, 46 insertions(+), 55 deletions(-) > > diff --git a/arch/arm/boot/dts/stih407-clock.dtsi b/arch/arm/boot/dts/stih407-clock.dtsi > index 9cce9541e26b..350bcfcf498b 100644 > --- a/arch/arm/boot/dts/stih407-clock.dtsi > +++ b/arch/arm/boot/dts/stih407-clock.dtsi > @@ -29,7 +29,7 @@ clocks { > */ > clockgen-a9@92b0000 { > compatible = "st,clkgen-c32"; > - reg = <0x92b0000 0xffff>; > + reg = <0x92b0000 0x10000>; > > clockgen_a9_pll: clockgen-a9-pll { > #clock-cells = <1>; > @@ -37,32 +37,27 @@ clockgen_a9_pll: clockgen-a9-pll { > > clocks = <&clk_sysin>; > }; > - }; > > - /* > - * ARM CPU related clocks. > - */ > - clk_m_a9: clk-m-a9@92b0000 { > - #clock-cells = <0>; > - compatible = "st,stih407-clkgen-a9-mux"; > - reg = <0x92b0000 0x10000>; > - > - clocks = <&clockgen_a9_pll 0>, > - <&clockgen_a9_pll 0>, > - <&clk_s_c0_flexgen 13>, > - <&clk_m_a9_ext2f_div2>; > + clk_m_a9: clk-m-a9 { > + #clock-cells = <0>; > + compatible = "st,stih407-clkgen-a9-mux"; > > + clocks = <&clockgen_a9_pll 0>, > + <&clockgen_a9_pll 0>, > + <&clk_s_c0_flexgen 13>, > + <&clk_m_a9_ext2f_div2>; > > - /* > - * ARM Peripheral clock for timers > - */ > - arm_periph_clk: clk-m-a9-periphs { > - #clock-cells = <0>; > - compatible = "fixed-factor-clock"; > + /* > + * ARM Peripheral clock for timers > + */ > + arm_periph_clk: clk-m-a9-periphs { > + #clock-cells = <0>; > + compatible = "fixed-factor-clock"; > > - clocks = <&clk_m_a9>; > - clock-div = <2>; > - clock-mult = <1>; > + clocks = <&clk_m_a9>; > + clock-div = <2>; > + clock-mult = <1>; > + }; > }; > }; > > @@ -87,14 +82,6 @@ clk_s_a0_flexgen: clk-s-a0-flexgen { > }; > }; > > - clk_s_c0_quadfs: clk-s-c0-quadfs@9103000 { > - #clock-cells = <1>; > - compatible = "st,quadfs-pll"; > - reg = <0x9103000 0x1000>; > - > - clocks = <&clk_sysin>; > - }; > - > clk_s_c0: clockgen-c@9103000 { > compatible = "st,clkgen-c32"; > reg = <0x9103000 0x1000>; > @@ -113,6 +100,13 @@ clk_s_c0_pll1: clk-s-c0-pll1 { > clocks = <&clk_sysin>; > }; > > + clk_s_c0_quadfs: clk-s-c0-quadfs { > + #clock-cells = <1>; > + compatible = "st,quadfs-pll"; > + > + clocks = <&clk_sysin>; > + }; > + > clk_s_c0_flexgen: clk-s-c0-flexgen { > #clock-cells = <1>; > compatible = "st,flexgen", "st,flexgen-stih407-c0"; > @@ -142,18 +136,17 @@ clk_m_a9_ext2f_div2: clk-m-a9-ext2f-div2s { > }; > }; > > - clk_s_d0_quadfs: clk-s-d0-quadfs@9104000 { > - #clock-cells = <1>; > - compatible = "st,quadfs-d0"; > - reg = <0x9104000 0x1000>; > - > - clocks = <&clk_sysin>; > - }; > - > clockgen-d0@9104000 { > compatible = "st,clkgen-c32"; > reg = <0x9104000 0x1000>; > > + clk_s_d0_quadfs: clk-s-d0-quadfs { > + #clock-cells = <1>; > + compatible = "st,quadfs-d0"; > + > + clocks = <&clk_sysin>; > + }; > + > clk_s_d0_flexgen: clk-s-d0-flexgen { > #clock-cells = <1>; > compatible = "st,flexgen", "st,flexgen-stih407-d0"; > @@ -166,18 +159,17 @@ clk_s_d0_flexgen: clk-s-d0-flexgen { > }; > }; > > - clk_s_d2_quadfs: clk-s-d2-quadfs@9106000 { > - #clock-cells = <1>; > - compatible = "st,quadfs-d2"; > - reg = <0x9106000 0x1000>; > - > - clocks = <&clk_sysin>; > - }; > - > clockgen-d2@9106000 { > compatible = "st,clkgen-c32"; > reg = <0x9106000 0x1000>; > > + clk_s_d2_quadfs: clk-s-d2-quadfs { > + #clock-cells = <1>; > + compatible = "st,quadfs-d2"; > + > + clocks = <&clk_sysin>; > + }; > + > clk_s_d2_flexgen: clk-s-d2-flexgen { > #clock-cells = <1>; > compatible = "st,flexgen", "st,flexgen-stih407-d2"; > @@ -192,18 +184,17 @@ clk_s_d2_flexgen: clk-s-d2-flexgen { > }; > }; > > - clk_s_d3_quadfs: clk-s-d3-quadfs@9107000 { > - #clock-cells = <1>; > - compatible = "st,quadfs-d3"; > - reg = <0x9107000 0x1000>; > - > - clocks = <&clk_sysin>; > - }; > - > clockgen-d3@9107000 { > compatible = "st,clkgen-c32"; > reg = <0x9107000 0x1000>; > > + clk_s_d3_quadfs: clk-s-d3-quadfs { > + #clock-cells = <1>; > + compatible = "st,quadfs-d3"; > + > + clocks = <&clk_sysin>; > + }; > + > clk_s_d3_flexgen: clk-s-d3-flexgen { > #clock-cells = <1>; > compatible = "st,flexgen", "st,flexgen-stih407-d3"; Reviewed-by: Patrice Chotard Thanks Patrice