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Mon, 08 Sep 2025 09:29:42 -0700 (PDT) X-Google-Smtp-Source: AGHT+IE8/ux+pl7ggDeP2V1/4IdQKuSpSB/3AQUQSSiAQ4GvrfZVtuHWRtKw2FqRwI/7hSQpSYGa7Q== X-Received: by 2002:a17:903:2b06:b0:24e:e5c9:ecf7 with SMTP id d9443c01a7336-25170c416ebmr108420405ad.34.1757348981586; Mon, 08 Sep 2025 09:29:41 -0700 (PDT) Received: from [10.91.118.43] ([202.46.23.19]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-329dcc0af56sm19952353a91.24.2025.09.08.09.29.37 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 08 Sep 2025 09:29:41 -0700 (PDT) Message-ID: Date: Mon, 8 Sep 2025 21:59:35 +0530 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2] drm/msm: adreno: a6xx: enable GMU bandwidth voting for x1e80100 GPU To: Konrad Dybcio , Dmitry Baryshkov Cc: Neil Armstrong , Rob Clark , Sean Paul , Konrad Dybcio , Dmitry Baryshkov , Abhinav Kumar , Jessica Zhang , Marijn Suijten , David Airlie , Simona Vetter , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org References: <20250725-topic-x1e80100-gpu-bwvote-v2-1-58d2fbb6a127@linaro.org> <33442cc4-a205-46a8-a2b8-5c85c236c8d4@oss.qualcomm.com> <269506b6-f51b-45cc-b7cc-7ad0e5ceea47@linaro.org> <1727374d-0461-4442-ab35-9acb8ef7f666@oss.qualcomm.com> <77db4861-4868-4110-8c31-eb2045ddbf4b@oss.qualcomm.com> <4fa44ec5-2792-45e3-af87-b3e4d2ed5d86@oss.qualcomm.com> From: Akhil P Oommen Content-Language: en-US In-Reply-To: <4fa44ec5-2792-45e3-af87-b3e4d2ed5d86@oss.qualcomm.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-Authority-Analysis: v=2.4 cv=FN4bx/os c=1 sm=1 tr=0 ts=68bf0477 cx=c_pps a=JL+w9abYAAE89/QcEU+0QA==:117 a=j4ogTh8yFefVWWEFDRgCtg==:17 a=IkcTkHD0fZMA:10 a=yJojWOMRYYMA:10 a=VwQbUJbxAAAA:8 a=EUspDBNiAAAA:8 a=KKAkSRfTAAAA:8 a=PfGohb2nDGJMFqWtIAwA:9 a=3ZKOabzyN94A:10 a=QEXdDO2ut3YA:10 a=324X-CrmTo6CU4MGRt3R:22 a=cvBusfyB2V15izCimMoJ:22 X-Proofpoint-ORIG-GUID: Tr9FaDIn8czrrV4XD_UjfabxRyIadhXV X-Proofpoint-GUID: Tr9FaDIn8czrrV4XD_UjfabxRyIadhXV X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwOTA4MDA5NCBTYWx0ZWRfX/VpyUBh+/+P9 A3tuO90VGrAwWQX4VHYGJwOMUM6b13idf+80Iy4J0HCBw1/z49BsDmnSfnY7CF3UrTh0fpwiHwd 8nawp4qR2/Jqcc/6JFq9tUTfS/3ZiyzG55uafqymoNORsxMCO9eRQ4fe0z8A6sIsSpKFoIL4mfZ PF3JwigG3HpFz1XonjldvWgavhsWvZnz+b9F6FzCT/M5hbNieiPfjpk6Yb/uXAYs0T4vkpcZqgQ +lZbpLdeRnqAXpp3n0/j5bz4ox0sUlhfEahXPrUSxxkfO825llHkenMTVMfzz9omSZvla3rbLmy Bn8VuxAaXFyBfrYEGMy0Gw6YExv0Anp8aGtfBkbF4xG4y4upQ9dqxnd02gFerl2dmc3b/hGjh+i aZ8H+ldc X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1117,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-09-08_06,2025-09-08_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 priorityscore=1501 clxscore=1015 phishscore=0 adultscore=0 bulkscore=0 impostorscore=0 malwarescore=0 suspectscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2507300000 definitions=main-2509080094 On 9/8/2025 9:52 PM, Konrad Dybcio wrote: > On 8/18/25 9:17 AM, Akhil P Oommen wrote: >> On 8/16/2025 3:45 AM, Dmitry Baryshkov wrote: >>> On Thu, Aug 14, 2025 at 07:52:13PM +0200, Konrad Dybcio wrote: >>>> On 8/14/25 6:38 PM, Akhil P Oommen wrote: >>>>> On 8/14/2025 7:56 PM, Neil Armstrong wrote: >>>>>> Hi, >>>>>> >>>>>> On 14/08/2025 13:22, Konrad Dybcio wrote: >>>>>>> On 8/14/25 1:21 PM, Konrad Dybcio wrote: >>>>>>>> On 7/31/25 12:19 PM, Konrad Dybcio wrote: >>>>>>>>> On 7/25/25 10:35 AM, Neil Armstrong wrote: >>>>>>>>>> The Adreno GPU Management Unit (GMU) can also scale DDR Bandwidth >>>>>>>>>> along >>>>>>>>>> the Frequency and Power Domain level, but by default we leave the >>>>>>>>>> OPP core scale the interconnect ddr path. >>>>>>>>>> >>>>>>>>>> Declare the Bus Control Modules (BCMs) and the corresponding >>>>>>>>>> parameters >>>>>>>>>> in the GPU info struct to allow the GMU to vote for the bandwidth. >>>>>>>>>> >>>>>>>>>> Reviewed-by: Dmitry Baryshkov >>>>>>>>>> Signed-off-by: Neil Armstrong >>>>>>>>>> --- >>>>>>>>>> Changes in v2: >>>>>>>>>> - Used proper ACV perfmode bit/freq >>>>>>>>>> - Link to v1: https://lore.kernel.org/r/20250721-topic-x1e80100- >>>>>>>>>> gpu-bwvote-v1-1-946619b0f73a@linaro.org >>>>>>>>>> --- >>>>>>>>>>   drivers/gpu/drm/msm/adreno/a6xx_catalog.c | 11 +++++++++++ >>>>>>>>>>   1 file changed, 11 insertions(+) >>>>>>>>>> >>>>>>>>>> diff --git a/drivers/gpu/drm/msm/adreno/a6xx_catalog.c b/drivers/ >>>>>>>>>> gpu/drm/msm/adreno/a6xx_catalog.c >>>>>>>>>> index >>>>>>>>>> 00e1afd46b81546eec03e22cda9e9a604f6f3b60..892f98b1f2ae582268adebd758437ff60456cdd5 100644 >>>>>>>>>> --- a/drivers/gpu/drm/msm/adreno/a6xx_catalog.c >>>>>>>>>> +++ b/drivers/gpu/drm/msm/adreno/a6xx_catalog.c >>>>>>>>>> @@ -1440,6 +1440,17 @@ static const struct adreno_info a7xx_gpus[] = { >>>>>>>>>>               .pwrup_reglist = &a7xx_pwrup_reglist, >>>>>>>>>>               .gmu_chipid = 0x7050001, >>>>>>>>>>               .gmu_cgc_mode = 0x00020202, >>>>>>>>>> +            .bcms = (const struct a6xx_bcm[]) { >>>>>>>>>> +                { .name = "SH0", .buswidth = 16 }, >>>>>>>>>> +                { .name = "MC0", .buswidth = 4 }, >>>>>>>>>> +                { >>>>>>>>>> +                    .name = "ACV", >>>>>>>>>> +                    .fixed = true, >>>>>>>>>> +                    .perfmode = BIT(3), >>>>>>>>>> +                    .perfmode_bw = 16500000, >>>>>>>>> >>>>>>>>> Reviewed-by: Konrad Dybcio >>>>>>>> >>>>>>>> Actually no, BIT(3) is for the CPU (OS), GPU should use BIT(2) >>>>> >>>>> You are right that BIT(2) is GPU specific, but that support was >>>>> commercialized from A7XX_GEN3. Anyway, the Win KMD uses BIT(2), so lets >>>>> use that in Linux too. >>>>> >>>>> I know some docs show BIT(2) support, but lets not bring in untested >>>>> configurations. >>>> >>>> Eh, then let's get the docs fixed if you don't trust them because we can't >>>> work like that.. >>>> >>>> FWIW this is information from per-platform RPMh cmd-db data >>> >>> If it comes from cmd-db, then we should be requesting it from the cmd-db >>> driver rather than hardcoding it here. > > No, what I meant is that there is a piece of configuration that reflects > what goes into cmd-db as its compiled and that's where I found that > information > >> >> Not really. This should be under the control of GPU driver. >> BIT(3) is correct for X1E. > > BIT(3) is for APPS, see the interconnect driver which also uses it. > This will create conflicts and may cause unvotes when some other > driver requests perf_mode through the ICC API, but the GPU is sitting > idle. No. GPU vote goes via a different DRV. So it is independent. Anyway, I checked this further earlier. X1E platform doesn't implement any perfmode vote. So both BIT(3) and BIT(2) are no-op and are ignored by AOSS. ICC driver's vote too should be no-op on X1E. -Akhil. > > Konrad