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Wed, 14 Oct 2026 09:45:51 -0700 (PDT) X-Received: by 2002:a05:620a:6501:b0:93a:1312:ff19 with SMTP id af79cd13be357-93ebd2661bdmr3238430085a.5.1791996350722; Wed, 14 Oct 2026 09:45:50 -0700 (PDT) Received: from [192.168.226.26] ([178.235.128.140]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-c3eda61fb26sm4954766b.69.2026.10.14.09.45.46 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 14 Oct 2026 09:45:49 -0700 (PDT) Message-ID: Date: Wed, 14 Oct 2026 18:45:46 +0200 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH RFC 07/16] clk: qcom: Add clock-owned GenPD DVFS aggregation To: Dmitry Baryshkov Cc: Konrad Dybcio , Stephen Boyd , Brian Masney , Jerome Brunet , Viresh Kumar , Nishanth Menon , "Rafael J. Wysocki" , Pavel Machek , Len Brown , Greg Kroah-Hartman , Danilo Krummrich , Johan Hovold , Ulf Hansson , Bjorn Andersson , Abel Vesa , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Neil Armstrong , Mike Tipton , Taniya Das , linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, driver-core@lists.linux.dev, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org References: <20261014-topic-qc_clk_dvfs-v1-0-3041b788e9f7@oss.qualcomm.com> <20261014-topic-qc_clk_dvfs-v1-7-3041b788e9f7@oss.qualcomm.com> <6c9937a6-88c3-4e5f-85a3-73d929d3ba01@oss.qualcomm.com> Content-Language: en-US From: Konrad Dybcio In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Proofpoint-ORIG-GUID: yD7BSWe1-Vm8vmpblzzwqmtasJMGlVJA X-Proofpoint-GUID: yD7BSWe1-Vm8vmpblzzwqmtasJMGlVJA X-Proofpoint-Spam-Info: AW1haW4tMjYxMDE0MDA2NiBTYWx0ZWRfX9WoyabNEpIro h7N2rMDsV6NgzP2gj6LPlC9h8XDmf+Fzw0OM0ynIiWF5K/Cwml5sZ/ie6FOyGek1IPZ/PPiq8ui Zb1PwIJk042GmQIzxTqmjfpOfBZFyq0= X-Authority-Analysis: v=2.4 cv=NctzRGD4 c=1 sm=1 tr=0 ts=6acfb1c0 cx=c_pps a=50t2pK5VMbmlHzFWWp8p/g==:117 a=PRfkaYvzSr8QmIIGAkY2Sg==:17 a=IkcTkHD0fZMA:10 a=660iZSQnnn4A:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=ZpdpYltYx_vBUK5n70dp:22 a=EUspDBNiAAAA:8 a=XY6eGlS5OATuIy7doj0A:9 a=QEXdDO2ut3YA:10 a=IoWCM6iH3mJn3m4BftBB:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYxMDE0MDA2NiBTYWx0ZWRfX7yjQe3IddLU7 1L7Gmruq4SpXWbAtT3H8eWmn7l9rqhbMebaEdW08nqRcojBImRxSkqlAHJ2wurELlZa9WQSU94k JSkee63Z1IuNbXBvOudXlDDfk0fdjhFw0/EgoRewWDO+iUgp9pHtj1cIJeQS02wlRnD+P+1OLAD JvwFp2UgRH5SWWyGlO2DpgUlPT4SR+nBSkOrHzFdQmGhVGZLlqooV56MsBwd5ga6efPLrMFS9+w 3pZfzSvvRo8TECdkCi22U03h+bMBs3GdYcjM6Y4Ps7KgCZVLEZrwq0ZTaNEVzW/oBlel17WaEzs mZu13tkrE76i/K1Rck2LO4MRKGqgUb0g+GIFfLyfGBl58uisdgmabf4EB3IAkLar4m4y1+6c2Hf 4TIIa9n2fwG4CDod0mpC0B6Sjv0eZwXXcxzOpwcQpA6oF7Qk1SgBBRR7TIrk0VKk6si7zg55Pql OHlkGHFu5HuxKq1qEeQ== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-10-13_01,2026-10-14_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 clxscore=1015 suspectscore=0 lowpriorityscore=0 spamscore=0 phishscore=0 impostorscore=0 bulkscore=0 malwarescore=0 adultscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2610080000 definitions=main-2610140066 On 10/14/26 6:30 PM, Dmitry Baryshkov wrote: > On Wed, Oct 14, 2026 at 05:26:00PM +0200, Konrad Dybcio wrote: >> On 10/14/26 4:36 PM, Dmitry Baryshkov wrote: >>> On Wed, Oct 14, 2026 at 02:19:07PM +0200, Konrad Dybcio wrote: >>>> From: Konrad Dybcio >>>> >>>> Clocks on Qualcomm SoCs need a minimum power rail performance state to >>>> operate at a given frequency. We currently leave this to clock >>>> consumers, so a driver has to know which power domains supply both the >>>> clock and its parents. This ties knowledge of the clock tree to >>>> individual consumers and doesn't protect other users that prepare or >>>> change the same clock without making those power requests. >>> >>> Why would they prepare or change the same clock without making power >>> requests? If it's a legitimate user of the clock, it should have an OPP >>> table. If it's not, it should have a separate API to set the clock via a >>> legitimate user / aggregator. >> >> That's the entire problem that motivated this series. The consumer >> doesn't know what it needs on Qualcomm platforms. The power >> requirements are that of the clock controller's, not of that device's. > > I'd still say that the consumers know that they need a certain > frequency, which demands a certain voltage / power / etc. Right, but the meaningful difference here is that the consumers only know they need a certain frequency. The required power votes from that don't stem from the consumer's requirements. They stem from the clock controller's inner workings that are necessary to fulfill the consumer's demand. [...] >> The Qualcomm case is easy - RPMH is *always* reachable, so the >> pmdomain provider needs no clocks itself. For the other cases, >> "patches welcome". > > Ok. There is a promise that I2C PMICs will never ever be involved in the > clock / power tables. Or at least that someone who needs them will contribute a solution to this problem. > >> >> [...] >> >>>> +static unsigned int >>>> +qcom_clk_dvfs_aggregate(struct qcom_clk_dvfs_rail_voter *rail_voter) >>>> +{ >>>> + struct qcom_clk_dvfs_vote *vote; >>>> + unsigned int level = 0; >>>> + >>>> + list_for_each_entry(vote, &rail_voter->votes, node) >>>> + level = max(level, vote->level); >>>> + >>>> + return max(level, rail_voter->safety_floor_level); >>> >>> I guess you want to avoid having too many voters, but would it be >>> possible to have one voter per 'signficant' clock and let GenPD itself >>> aggregate all the votes? >> >> What does "significant" mean here? > > I'd define it as "using a different power domain or requiring a > different corner". I still don't get it Konrad