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([2001:b07:6468:f312:24f5:23b:4085:b879]) by smtp.gmail.com with ESMTPSA id 67sm22498925wrk.49.2020.06.23.02.50.08 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 23 Jun 2020 02:50:09 -0700 (PDT) Subject: Re: [PATCH] KVM: X86: Fix MSR range of APIC registers in X2APIC mode To: Xiaoyao Li , Sean Christopherson , Vitaly Kuznetsov , Jim Mattson Cc: kvm@vger.kernel.org, linux-kernel@vger.kernel.org References: <20200616073307.16440-1-xiaoyao.li@intel.com> From: Paolo Bonzini Message-ID: Date: Tue, 23 Jun 2020 11:50:07 +0200 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.6.0 MIME-Version: 1.0 In-Reply-To: <20200616073307.16440-1-xiaoyao.li@intel.com> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 7bit Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 16/06/20 09:33, Xiaoyao Li wrote: > Only MSR address range 0x800 through 0x8ff is architecturally reserved > and dedicated for accessing APIC registers in x2APIC mode. > > Fixes: 0105d1a52640 ("KVM: x2apic interface to lapic") > Signed-off-by: Xiaoyao Li > --- > arch/x86/kvm/x86.c | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) > > diff --git a/arch/x86/kvm/x86.c b/arch/x86/kvm/x86.c > index 00c88c2f34e4..29d9b078ce69 100644 > --- a/arch/x86/kvm/x86.c > +++ b/arch/x86/kvm/x86.c > @@ -2856,7 +2856,7 @@ int kvm_set_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info) > return kvm_mtrr_set_msr(vcpu, msr, data); > case MSR_IA32_APICBASE: > return kvm_set_apic_base(vcpu, msr_info); > - case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff: > + case APIC_BASE_MSR ... APIC_BASE_MSR + 0xff: > return kvm_x2apic_msr_write(vcpu, msr, data); > case MSR_IA32_TSCDEADLINE: > kvm_set_lapic_tscdeadline_msr(vcpu, data); > @@ -3196,7 +3196,7 @@ int kvm_get_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info) > case MSR_IA32_APICBASE: > msr_info->data = kvm_get_apic_base(vcpu); > break; > - case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff: > + case APIC_BASE_MSR ... APIC_BASE_MSR + 0xff: > return kvm_x2apic_msr_read(vcpu, msr_info->index, &msr_info->data); > case MSR_IA32_TSCDEADLINE: > msr_info->data = kvm_get_lapic_tscdeadline_msr(vcpu); > Queued, thanks (with Cc to stable). Paolo