From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.0 required=3.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY, SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id B880EC04EB8 for ; Sun, 2 Dec 2018 20:24:43 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 72B6820851 for ; Sun, 2 Dec 2018 20:24:43 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="T2skOmWU" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 72B6820851 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726062AbeLBUYp (ORCPT ); Sun, 2 Dec 2018 15:24:45 -0500 Received: from mail-wr1-f67.google.com ([209.85.221.67]:45375 "EHLO mail-wr1-f67.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725984AbeLBUYp (ORCPT ); Sun, 2 Dec 2018 15:24:45 -0500 Received: by mail-wr1-f67.google.com with SMTP id v6so10023020wrr.12; Sun, 02 Dec 2018 12:24:39 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=9WG2eU/ejG4wAWToKoueA27/6ygzN1rLZLWAo8LIhNE=; b=T2skOmWUlvAkqf6eBm9og5ZfS9jT1KI23fo/nbKhhS856UmFfaUb8HwHgXouxyXthM sqoQ7sQP2T4sVDfkt+m/FOjxKdEwXC4uMOTqofGMZYfg3pHItllfWhd26mB9eeFbg1FC nN8elPRFBkCLS6+x3mMhqyVYB4IsnEhDMk/0nXmBVrB1rp60vpT4pxOmsdScTjjoTt0g y78LIjXNmm/ATEgZSit7wigak9HNNVPqEVJRruahzGnjCn0FOLQ6vzdxjgLU1ywH5ecz BitLT4LVFASPkDx3Wt9iVEtDFmlGMWFDqasRXxj9y8vnUwe9x/Y/fMBNhUSVPS8aSJwF OL0w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=9WG2eU/ejG4wAWToKoueA27/6ygzN1rLZLWAo8LIhNE=; b=Cp8lRJWWA6rXts9843l9AEzwUoYFHv2CT7NbZjcS+785DdBIIr90w5pweqfMxWJlVV RyagDJT57wvWbqfysqnJx0MymIznp8x0dPXt1EKMVCj22rtjVSuV8iMx/LkPO0+ShmHC vQCTrUUtal1s8DBtsqIGN3R9HD/mo1mNhvpIXZSH5y9faeq6k6oLhfCor9TytBU0pIp1 RNu3tbt2pYDHrebnU5GUhLdWbBl5i3CP5qv9fAlz9xzkBH72rohQx1t9PImQHrIdYAZr EQYtDGGSQ3vep+EDz94P1ZgahYuRCZbLobgaXS2H0BEycTOVDaHfyTYx8AuUSMQl5RDO RHyg== X-Gm-Message-State: AA+aEWZnJu+3YZtzlX9Ar/1eigoUoNMM9QZDgU37Jhn1fQznlNxePDm/ A1LNTCgR0FVLoD/6mV6ncvqAMMITPYE= X-Google-Smtp-Source: AFSGD/XRntLJPSM0w/Zsn7h1n0X9PgvCcz+6P5fwxaPwEuoO7d0rpyeQLePdNF9RAuMCz6TteCsl2Q== X-Received: by 2002:adf:82e4:: with SMTP id 91mr12176031wrc.131.1543782278799; Sun, 02 Dec 2018 12:24:38 -0800 (PST) Received: from ThinkPad.home ([185.219.177.152]) by smtp.gmail.com with ESMTPSA id l3sm14451510wma.44.2018.12.02.12.24.37 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Sun, 02 Dec 2018 12:24:38 -0800 (PST) From: Mesih Kilinc To: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-gpio@vger.kernel.org, linux-sunxi@googlegroups.com Cc: Mesih Kilinc , Maxime Ripard , Chen-Yu Tsai , Russell King , Daniel Lezcano , Marc Zyngier , Linus Walleij , Icenowy Zheng , Rob Herring , Julian Calaby Subject: [PATCH v6 16/17] ARM: dts: suniv: add initial DTSI file for F1C100s Date: Sun, 2 Dec 2018 23:23:50 +0300 Message-Id: X-Mailer: git-send-email 2.7.4 In-Reply-To: References: Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org F1C100s is one product with the suniv die, which has a 32MiB co-packaged DDR1 DRAM chip. As we have the support for suniv pin controller and CCU now, add a initial DTSI for it. Signed-off-by: Mesih Kilinc --- arch/arm/boot/dts/suniv-f1c100s.dtsi | 147 +++++++++++++++++++++++++++++++++++ 1 file changed, 147 insertions(+) create mode 100644 arch/arm/boot/dts/suniv-f1c100s.dtsi diff --git a/arch/arm/boot/dts/suniv-f1c100s.dtsi b/arch/arm/boot/dts/suniv-f1c100s.dtsi new file mode 100644 index 0000000..aff5f90 --- /dev/null +++ b/arch/arm/boot/dts/suniv-f1c100s.dtsi @@ -0,0 +1,147 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR X11) +/* + * Copyright 2018 Icenowy Zheng + * Copyright 2018 Mesih Kilinc + */ + +#include +#include + +/ { + #address-cells = <1>; + #size-cells = <1>; + interrupt-parent = <&intc>; + + clocks { + osc24M: clk-24M { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <24000000>; + clock-output-names = "osc24M"; + }; + + osc32k: clk-32k { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <32768>; + clock-output-names = "osc32k"; + }; + }; + + cpus { + cpu { + compatible = "arm,arm926ej-s"; + device_type = "cpu"; + }; + }; + + soc { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + sram-controller@1c00000 { + compatible = "allwinner,suniv-f1c100s-system-control", + "allwinner,sun4i-a10-system-control"; + reg = <0x01c00000 0x30>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + sram_d: sram@10000 { + compatible = "mmio-sram"; + reg = <0x00010000 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x00010000 0x1000>; + + otg_sram: sram-section@0 { + compatible = "allwinner,suniv-f1c100s-sram-d", + "allwinner,sun4i-a10-sram-d"; + reg = <0x0000 0x1000>; + status = "disabled"; + }; + }; + }; + + ccu: clock@1c20000 { + compatible = "allwinner,suniv-f1c100s-ccu"; + reg = <0x01c20000 0x400>; + clocks = <&osc24M>, <&osc32k>; + clock-names = "hosc", "losc"; + #clock-cells = <1>; + #reset-cells = <1>; + }; + + intc: interrupt-controller@1c20400 { + compatible = "allwinner,suniv-f1c100s-ic"; + reg = <0x01c20400 0x400>; + interrupt-controller; + #interrupt-cells = <1>; + }; + + pio: pinctrl@1c20800 { + compatible = "allwinner,suniv-f1c100s-pinctrl"; + reg = <0x01c20800 0x400>; + interrupts = <38>, <39>, <40>; + clocks = <&ccu 37>, <&osc24M>, <&osc32k>; + clock-names = "apb", "hosc", "losc"; + gpio-controller; + interrupt-controller; + #interrupt-cells = <3>; + #gpio-cells = <3>; + + uart0_pe_pins: uart0-pe-pins { + pins = "PE0", "PE1"; + function = "uart0"; + }; + }; + + timer@1c20c00 { + compatible = "allwinner,suniv-f1c100s-timer"; + reg = <0x01c20c00 0x90>; + interrupts = <13>; + clocks = <&osc24M>; + }; + + wdt: watchdog@1c20ca0 { + compatible = "allwinner,suniv-f1c100s-wdt", + "allwinner,sun4i-a10-wdt"; + reg = <0x01c20ca0 0x20>; + }; + + uart0: serial@1c25000 { + compatible = "snps,dw-apb-uart"; + reg = <0x01c25000 0x400>; + interrupts = <1>; + reg-shift = <2>; + reg-io-width = <4>; + clocks = <&ccu 38>; + resets = <&ccu 24>; + status = "disabled"; + }; + + uart1: serial@1c25400 { + compatible = "snps,dw-apb-uart"; + reg = <0x01c25400 0x400>; + interrupts = <2>; + reg-shift = <2>; + reg-io-width = <4>; + clocks = <&ccu 39>; + resets = <&ccu 25>; + status = "disabled"; + }; + + uart2: serial@1c25800 { + compatible = "snps,dw-apb-uart"; + reg = <0x01c25800 0x400>; + interrupts = <3>; + reg-shift = <2>; + reg-io-width = <4>; + clocks = <&ccu 40>; + resets = <&ccu 26>; + status = "disabled"; + }; + }; +}; -- 2.7.4