Re: [PATCH V2 7/7] coresight: trbe: Work around the trace data corruption

[Suzuki K Poulose <suzuki.poulose@arm.com>]

On 07/01/2022 01:10, Anshuman Khandual wrote:
> TRBE implementations affected by Arm erratum #1902691 might corrupt trace
> data or deadlock, when it's being written into the memory. Workaround this
> problem in the driver, by preventing TRBE initialization on affected cpus.
> The firmware must have disabled the access to TRBE for the kernel on such
> implementations. This will cover the kernel for any firmware that doesn't
> do this already. This just updates the TRBE driver as required.
> 
> Cc: Catalin Marinas <catalin.marinas@arm.com>
> Cc: Will Deacon <will@kernel.org>
> Cc: Mathieu Poirier <mathieu.poirier@linaro.org>
> Cc: Suzuki Poulose <suzuki.poulose@arm.com>
> Cc: coresight@lists.linaro.org
> Cc: linux-doc@vger.kernel.org
> Cc: linux-arm-kernel@lists.infradead.org
> Cc: linux-kernel@vger.kernel.org
> Signed-off-by: Anshuman Khandual <anshuman.khandual@arm.com>
> ---
>   arch/arm64/Kconfig                           |  2 +-
>   drivers/hwtracing/coresight/coresight-trbe.c | 12 ++++++++++++
>   2 files changed, 13 insertions(+), 1 deletion(-)
> 
> diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig
> index 209e481acf0d..8a2245c3e857 100644
> --- a/arch/arm64/Kconfig
> +++ b/arch/arm64/Kconfig
> @@ -821,7 +821,7 @@ config ARM64_ERRATUM_2038923
>   
>   config ARM64_ERRATUM_1902691
>   	bool "Cortex-A510: 1902691: workaround TRBE trace corruption"
> -	depends on COMPILE_TEST # Until the CoreSight TRBE driver changes are in
> +	depends on CORESIGHT_TRBE
>   	default y
>   	help
>   	  This option adds the workaround for ARM Cortex-A510 erratum 1902691.
> diff --git a/drivers/hwtracing/coresight/coresight-trbe.c b/drivers/hwtracing/coresight/coresight-trbe.c
> index c4cc529749f8..d2f1c68e589c 100644
> --- a/drivers/hwtracing/coresight/coresight-trbe.c
> +++ b/drivers/hwtracing/coresight/coresight-trbe.c
> @@ -93,12 +93,14 @@ struct trbe_buf {
>   #define TRBE_WORKAROUND_WRITE_OUT_OF_RANGE	1
>   #define TRBE_NEEDS_DRAIN_AFTER_DISABLE		2
>   #define TRBE_NEEDS_CTXT_SYNC_AFTER_ENABLE	3
> +#define TRBE_IS_BROKEN				4
>   
>   static int trbe_errata_cpucaps[] = {
>   	[TRBE_WORKAROUND_OVERWRITE_FILL_MODE] = ARM64_WORKAROUND_TRBE_OVERWRITE_FILL_MODE,
>   	[TRBE_WORKAROUND_WRITE_OUT_OF_RANGE] = ARM64_WORKAROUND_TRBE_WRITE_OUT_OF_RANGE,
>   	[TRBE_NEEDS_DRAIN_AFTER_DISABLE] = ARM64_WORKAROUND_2064142,
>   	[TRBE_NEEDS_CTXT_SYNC_AFTER_ENABLE] = ARM64_WORKAROUND_2038923,
> +	[TRBE_IS_BROKEN] = ARM64_WORKAROUND_1902691,
>   	-1,		/* Sentinel, must be the last entry */
>   };
>   
> @@ -181,6 +183,11 @@ static inline bool trbe_needs_ctxt_sync_after_enable(struct trbe_cpudata *cpudat
>   	return trbe_has_erratum(cpudata, TRBE_NEEDS_CTXT_SYNC_AFTER_ENABLE);
>   }
>   
> +static inline bool trbe_is_broken(struct trbe_cpudata *cpudata)
> +{
> +	return trbe_has_erratum(cpudata, TRBE_IS_BROKEN);
> +}
> +
>   static int trbe_alloc_node(struct perf_event *event)
>   {
>   	if (event->cpu == -1)
> @@ -1288,6 +1295,11 @@ static void arm_trbe_probe_cpu(void *info)
>   	 */
>   	trbe_check_errata(cpudata);
>   
> +	if (trbe_is_broken(cpudata)) {
> +		pr_err("Disabling TRBE on cpu%d due to erratum\n", cpu);
> +		goto cpu_clear;
> +	}
> +
>   	/*
>   	 * If the TRBE is affected by erratum TRBE_WORKAROUND_OVERWRITE_FILL_MODE,
>   	 * we must always program the TBRPTR_EL1, 256bytes from a page


Reviewed-by: Suzuki K Poulose <suzuki.poulose@arm.com>