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charset=UTF-8 Content-Transfer-Encoding: 7bit X-Authority-Analysis: v=2.4 cv=PIs/P/qC c=1 sm=1 tr=0 ts=6a280fbf cx=c_pps a=P2rfLEam3zuxRRdjJWA2cw==:117 a=PRfkaYvzSr8QmIIGAkY2Sg==:17 a=IkcTkHD0fZMA:10 a=FelO9ux0wxsA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=ZpdpYltYx_vBUK5n70dp:22 a=VaM7kzH05nLpQn4dOD8A:9 a=QEXdDO2ut3YA:10 a=ODZdjJIeia2B_SHc_B0f:22 X-Proofpoint-GUID: 8mQfAVpfFXnASvIcjLpOA2djlv82M_Mq X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNjA5MDEyNCBTYWx0ZWRfX4tBFE+p8lh48 E4vxVtRfeaX2pYKZL7F+ezHxbtq1g1gZzILYAcHly9PR91uNAhbcK98GpzSDfl0lL2/DQo5hsyH EofDwF04DM4I+uSgdEY+db8zkek1jUIqf2lfeIUtIUpVE21FiXWsCnXXeee95J6OuW/NM4rbXeD LyVSUSFbps4nmcjEjK3LAlyPSEsXDkyd7gY+djZ/TKf7CagIUil9a4mz2ORUzbOAN57yevx8gpC MxCG1fA33yJ400CB0NYRQsXvb3a3Q7OQ90Nsb8sq65NJOohe4erOaMGTgr2fK7iZUWHXpvekP/t os8Qe9eqE8opp6FMIhC24ci0ZEafb7T10H1j9mQOQjxdfAlV0N49+j5jGtBbmN2/yovNij5xBCt Rjqm2S5JWD1Kykjf9oC8nKwCfMhz9soRK30adyk+Gz7WF8yQAm6xTvvOcjdrNReMnzdgoEvjC5K p/uwABSd357D0psAfIw== X-Proofpoint-ORIG-GUID: 8mQfAVpfFXnASvIcjLpOA2djlv82M_Mq X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.125,FMLib:17.12.100.49 definitions=2026-06-09_03,2026-06-09_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 phishscore=0 impostorscore=0 suspectscore=0 adultscore=0 spamscore=0 clxscore=1015 malwarescore=0 priorityscore=1501 bulkscore=0 lowpriorityscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2605210000 definitions=main-2606090124 On 5/28/26 4:29 AM, Qiang Yu wrote: > PCIe5 PHY on Mahua gets refclk from CXO0 pad directly, so no QREF > clkref_en voting is required. Override the clock list to use RPMH_CXO_CLK > directly instead. This is the last piece of the puzzle that this series is missing. There's no QREF clkref_en, but there is a refgen that needs to be powered. For PCIe5 on Mahua this would be L2F_E0 (0p9) and L4H_E0 (1p2). I think the easiest (laziest?) solution would be to add dummy clocks in the clkref driver and only toggle the required regulators. Another option is to defer back to individual drivers (such as PCIe QMPPHY). I kinda like the "one central node to drive power" approach, but I'm not sure others agree, since it stretches truth just a tiny bit (although not as much as one would think since there are *some* controls for the transparent-to-the-OS hw pieces in these paths still in TCSR).. Dmitry, Krzysztof, would you object to that? Konrad