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From: Suzuki K Poulose <Suzuki.Poulose@arm.com>
To: Mathieu Poirier <mathieu.poirier@linaro.org>
Cc: linux-arm-kernel@lists.infradead.org,
	linux-kernel@vger.kernel.org, rob.walker@arm.com,
	mike.leach@linaro.org, coresight@lists.linaro.org
Subject: Re: [PATCH 06/17] coresight: tmc: Make ETR SG table circular
Date: Thu, 2 Nov 2017 12:00:51 +0000	[thread overview]
Message-ID: <db0a9a62-e2b5-6895-f7b9-42989d3d56e2@arm.com> (raw)
In-Reply-To: <20171101234717.GA16611@xps15>

On 01/11/17 23:47, Mathieu Poirier wrote:
> On Thu, Oct 19, 2017 at 06:15:42PM +0100, Suzuki K Poulose wrote:
>> Make the ETR SG table Circular buffer so that we could start
>> at any of the SG pages and use the entire buffer for tracing.
>> This can be achieved by :
>>
>> 1) Keeping an additional LINK pointer at the very end of the
>> SG table, i.e, after the LAST buffer entry, to point back to
>> the beginning of the first table. This will allow us to use
>> the buffer normally when we start the trace at offset 0 of
>> the buffer, as the LAST buffer entry hints the TMC-ETR and
>> it automatically wraps to the offset 0.
>>
>> 2) If we want to start at any other ETR SG page aligned offset,
>> we could :
>>   a) Make the preceding page entry as LAST entry.
>>   b) Make the original LAST entry a normal entry.
>>   c) Use the table pointer to the "new" start offset as the
>>      base of the table address.
>> This works as the TMC doesn't mandate that the page table
>> base address should be 4K page aligned.
>>
>> Cc: Mathieu Poirier <mathieu.poirier@linaro.org>
>> Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
>> ---

>> +static int __maybe_unused
>> +tmc_etr_sg_table_rotate(struct etr_sg_table *etr_table, u64 base_offset)
>> +{
>> +	u32 last_entry, first_entry;
>> +	u64 last_offset;
>> +	struct tmc_sg_table *sg_table = etr_table->sg_table;
>> +	sgte_t *table_ptr = sg_table->table_vaddr;
>> +	ssize_t buf_size = tmc_sg_table_buf_size(sg_table);
>> +
>> +	/* Offset should always be SG PAGE_SIZE aligned */
>> +	if (base_offset & (ETR_SG_PAGE_SIZE - 1)) {
>> +		pr_debug("unaligned base offset %llx\n", base_offset);
>> +		return -EINVAL;
>> +	}
>> +	/* Make sure the offset is within the range */
>> +	if (base_offset < 0 || base_offset > buf_size) {
>> +		base_offset = (base_offset + buf_size) % buf_size;
>> +		pr_debug("Resetting offset to %llx\n", base_offset);
>> +	}
>> +	first_entry = tmc_etr_sg_offset_to_table_index(base_offset);
>> +	if (first_entry == etr_table->first_entry) {
>> +		pr_debug("Head is already at %llx, skipping\n", base_offset);
>> +		return 0;
>> +	}
>> +
>> +	/* Last entry should be the previous one to the new "base" */
>> +	last_offset = ((base_offset - ETR_SG_PAGE_SIZE) + buf_size) % buf_size;
>> +	last_entry = tmc_etr_sg_offset_to_table_index(last_offset);
>> +
>> +	/* Reset the current Last page to Normal and new Last page to NORMAL */
>> +	tmc_etr_sg_update_type(&table_ptr[etr_table->last_entry],
>> +				 ETR_SG_ET_NORMAL);
>> +	tmc_etr_sg_update_type(&table_ptr[last_entry], ETR_SG_ET_LAST);
>> +	etr_table->hwaddr = tmc_etr_sg_table_index_to_daddr(sg_table,
>> +							    first_entry);
>> +	etr_table->first_entry = first_entry;
>> +	etr_table->last_entry = last_entry;
>> +	pr_debug("table rotated to offset %llx-%llx, entries (%d - %d), dba: %llx\n",
>> +			base_offset, last_offset, first_entry, last_entry,
>> +			etr_table->hwaddr);
> 
> The above line generates a warning when compiling for ARMv7.

Where you running with LPAE off ? That could probably be the case,
where hwaddr could be 32bit or 64bit depending on whether LPAE
is enabled. I will fix it.

I have fixed some other warnings with ARMv7 with LPAE.

Suzuki

  reply	other threads:[~2017-11-02 12:00 UTC|newest]

Thread overview: 56+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2017-10-19 17:15 [PATCH 00/17] coresight: perf: TMC ETR backend support Suzuki K Poulose
2017-10-19 17:15 ` [PATCH 01/17] coresight etr: Disallow perf mode temporarily Suzuki K Poulose
2017-10-19 17:15 ` [PATCH 02/17] coresight tmc: Hide trace buffer handling for file read Suzuki K Poulose
2017-10-20 12:34   ` Julien Thierry
2017-11-01  9:55     ` Suzuki K Poulose
2017-10-19 17:15 ` [PATCH 03/17] coresight: Add helper for inserting synchronization packets Suzuki K Poulose
2017-10-30 21:44   ` Mathieu Poirier
2017-11-01 10:01     ` Suzuki K Poulose
2017-10-19 17:15 ` [PATCH 04/17] coresight: Add generic TMC sg table framework Suzuki K Poulose
2017-10-31 22:13   ` Mathieu Poirier
2017-11-01 10:09     ` Suzuki K Poulose
2017-10-19 17:15 ` [PATCH 05/17] coresight: Add support for TMC ETR SG unit Suzuki K Poulose
2017-10-20 16:25   ` Julien Thierry
2017-11-01 10:11     ` Suzuki K Poulose
2017-11-01 20:41   ` Mathieu Poirier
2017-10-19 17:15 ` [PATCH 06/17] coresight: tmc: Make ETR SG table circular Suzuki K Poulose
2017-10-20 17:11   ` Julien Thierry
2017-11-01 10:12     ` Suzuki K Poulose
2017-11-01 23:47   ` Mathieu Poirier
2017-11-02 12:00     ` Suzuki K Poulose [this message]
2017-11-02 14:40       ` Mathieu Poirier
2017-11-02 15:13         ` Russell King - ARM Linux
2017-11-06 19:07   ` Mathieu Poirier
2017-11-07 10:36     ` Suzuki K Poulose
2017-11-09 16:19       ` Mathieu Poirier
2017-10-19 17:15 ` [PATCH 07/17] coresight: tmc etr: Add transparent buffer management Suzuki K Poulose
2017-11-02 17:48   ` Mathieu Poirier
2017-11-03 10:02     ` Suzuki K Poulose
2017-11-03 20:13       ` Mathieu Poirier
2017-10-19 17:15 ` [PATCH 08/17] coresight: tmc: Add configuration support for trace buffer size Suzuki K Poulose
2017-11-02 19:26   ` Mathieu Poirier
2017-10-19 17:15 ` [PATCH 09/17] coresight: Convert driver messages to dev_dbg Suzuki K Poulose
2017-10-19 17:15 ` [PATCH 10/17] coresight: etr: Track if the device is coherent Suzuki K Poulose
2017-11-02 19:40   ` Mathieu Poirier
2017-11-03 10:03     ` Suzuki K Poulose
2017-10-19 17:15 ` [PATCH 11/17] coresight etr: Handle driver mode specific ETR buffers Suzuki K Poulose
2017-11-02 20:26   ` Mathieu Poirier
2017-11-03 10:08     ` Suzuki K Poulose
2017-11-03 20:30       ` Mathieu Poirier
2017-10-19 17:15 ` [PATCH 12/17] coresight etr: Relax collection of trace from sysfs mode Suzuki K Poulose
2017-10-19 17:15 ` [PATCH 13/17] coresight etr: Do not clean ETR trace buffer Suzuki K Poulose
2017-11-02 20:36   ` Mathieu Poirier
2017-11-03 10:10     ` Suzuki K Poulose
2017-11-03 20:17       ` Mathieu Poirier
2017-11-07 10:37         ` Suzuki K Poulose
2017-10-19 17:15 ` [PATCH 14/17] coresight: etr: Add support for save restore buffers Suzuki K Poulose
2017-11-03 22:22   ` Mathieu Poirier
2017-10-19 17:15 ` [PATCH 15/17] coresight: etr_buf: Add helper for padding an area of trace data Suzuki K Poulose
2017-10-19 17:15 ` [PATCH 16/17] coresight: perf: Remove reset_buffer call back for sinks Suzuki K Poulose
2017-11-06 21:10   ` Mathieu Poirier
2017-10-19 17:15 ` [PATCH 17/17] coresight perf: Add ETR backend support for etm-perf Suzuki K Poulose
2017-11-07  0:24   ` Mathieu Poirier
2017-11-07 10:52     ` Suzuki K Poulose
2017-11-07 15:17       ` Mike Leach
2017-11-07 15:46         ` Mathieu Poirier
2017-10-20 11:00 ` [PATCH 00/17] coresight: perf: TMC ETR backend support Suzuki K Poulose

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