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[2001:14ba:a0db:1f00::8a5]) by smtp.gmail.com with ESMTPSA id a15-20020a05651c010f00b002ad988efd73sm343073ljb.14.2023.05.08.17.48.40 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 08 May 2023 17:48:40 -0700 (PDT) Message-ID: Date: Tue, 9 May 2023 03:48:40 +0300 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.10.0 Subject: Re: [PATCH v2 3/4] drm/msm/dpu: Add DPU_INTF_DATA_COMPRESS feature flag Content-Language: en-GB To: Abhinav Kumar , Jessica Zhang , Marijn Suijten Cc: Rob Clark , Sean Paul , David Airlie , Daniel Vetter , Konrad Dybcio , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org References: <20230405-add-dsc-support-v2-0-1072c70e9786@quicinc.com> <20230405-add-dsc-support-v2-3-1072c70e9786@quicinc.com> <1d7ccb5f-55c2-3b3a-df97-2c17beffabfc@quicinc.com> <0aa4130d-bb37-4743-10e5-fd518276f4a2@linaro.org> <9aad0f0a-f168-5162-68a0-9e9cde21c1f6@quicinc.com> From: Dmitry Baryshkov In-Reply-To: <9aad0f0a-f168-5162-68a0-9e9cde21c1f6@quicinc.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 09/05/2023 03:28, Abhinav Kumar wrote: > > > On 5/8/2023 4:08 PM, Dmitry Baryshkov wrote: >> On 09/05/2023 00:46, Jessica Zhang wrote: >>> >>> >>> On 5/7/2023 9:00 AM, Marijn Suijten wrote: >>>> On 2023-05-05 14:23:50, Jessica Zhang wrote: >>>>> Add DATA_COMPRESS feature flag to DPU INTF block. >>>>> >>>>> In DPU 7.x and later, DSC/DCE enablement registers have been moved >>>>> from >>>>> PINGPONG to INTF. >>>>> >>>>> As core_rev (and related macros) was removed from the dpu_kms >>>>> struct, the >>>>> most straightforward way to indicate the presence of this register >>>>> would be >>>>> to have a feature flag. >>>> >>>> Irrelevant.  Even though core_rev was still in mainline until recently, >>>> we always hardcoded the features in the catalog and only used core_rev >>>> to select a dpu_mdss_cfg catalog entry.  There is no "if version >= X >>>> then enable feature Y" logic, this manually-enabled feature flag is the >>>> only, correct way to do it. >>> >>> Hi Marijn, >>> >>> Understood. FWIW, if we do find more register bit-level differences >>> between HW versions in the future, it might make more sense to keep >>> the HW catalog small and bring core_rev back, rather than keep adding >>> these kinds of small differences to caps. >> >> Let's see how it goes. Abhinav suggested that there might be feature >> differences inside the DPU generations (and even inside the single DPU >> major/minor combo). So I'm not sure what core_rev will bring us. >> > > It allows us to have if MDSS_REV() checks which are convenient for some > calculations / bit programming which we dont want to expose in the > catalog as they cannot be classified as a hw cap as such or atleast we > dont want them to be classified as such. > >> Let's land the platforms which are ready (or if there is anything >> close to be submitted). I'll post the next proposal for the catalog >> cleanups close to -rc4, when the dust settles then we can have one or >> two weaks for the discussion and polishing. >> >> I'd like to consider: >> - inlining foo_BLK macros, if that makes adding new features easier >> - reformat of clk_ctrls >> - maybe reintroduction of per-generation feature masks instead of >> keeping them named after the random SoC >> - maybe a rework of mdss_irqs / INTFn_INTR. We already have this info >> in hw catalog. >> >> Comments are appreciated. >> > > I would say, lets wait for DSC to settle. Atleast the parts already on > the list. Continuous rebase of features already on the list is becoming > time consuming because of overlapping catalog reworks. As I wrote, -rc4. Until that time, I'd expect DSC to be settled and accepted. -- With best wishes Dmitry