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charset="UTF-8"; format=flowed Content-Transfer-Encoding: 7bit X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nasanex01b.na.qualcomm.com (10.46.141.250) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: 53KUHXRXMg_U-w1wGFJp9ve0aqlWp6mS X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNzAxMDA3NSBTYWx0ZWRfXydNpWbOOQGf1 Wv+siRXa/2cbh3Z8Eot4kcDX+2h6b7kX/JioCBVsghq5jUWr9KcDnW5swNqBn7tC/bCiizQf5ca vQAtClfnilZtupqGfVaV10qNUocag9nSM+OqIrsY+BnxqFZhMoxb2RK3ijlo4Af5WvOsNAlkNyk gx2Yqd++S5ol6Gk7G5vV0lt55rJJL6BBkVUQeGG6IselcbCmRlT2Y1VLZawJb78I1N+74wkBEEn EcbGm+PxV+fzTwHfyL54oq3owHMNU09Pnr7uYJTKm+NzA5nVSkpT/d+9Qkycd1j2GKkKIPgxVUB goqX4dVBlCVkYg4viZedXrBnozlZazfIbDBtrvtaUWbhlRU1R8tDm53kms2igQ8m2pz+vdUjLlx RlTAuD61CHme3I6B9dxnjgYmhOuW6Mmc2VEn12Z3kZ4quTdjED7pqLDovWrEL1M0uHNBwLl9 X-Authority-Analysis: v=2.4 cv=L9sdQ/T8 c=1 sm=1 tr=0 ts=6863cfc6 cx=c_pps a=JYp8KDb2vCoCEuGobkYCKw==:117 a=JYp8KDb2vCoCEuGobkYCKw==:17 a=GEpy-HfZoHoA:10 a=IkcTkHD0fZMA:10 a=Wb1JkmetP80A:10 a=COk6AnOGAAAA:8 a=EUspDBNiAAAA:8 a=8K8LTxnoByzQzqUqCa4A:9 a=QEXdDO2ut3YA:10 a=TjNXssC_j7lpFel5tvFf:22 X-Proofpoint-GUID: 53KUHXRXMg_U-w1wGFJp9ve0aqlWp6mS X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.1.7,FMLib:17.12.80.40 definitions=2025-07-01_02,2025-06-27_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 spamscore=0 phishscore=0 impostorscore=0 priorityscore=1501 malwarescore=0 lowpriorityscore=0 adultscore=0 suspectscore=0 mlxlogscore=999 bulkscore=0 mlxscore=0 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2505280000 definitions=main-2507010075 On 6/28/2025 12:27 AM, Konrad Dybcio wrote: > On 6/27/25 2:09 PM, Luo Jie wrote: >> NSS clock controller provides the clocks and resets to the networking >> hardware blocks on the IPQ5424, such as PPE (Packet Process Engine) and >> UNIPHY (PCS) blocks. >> >> Signed-off-by: Luo Jie >> --- >> arch/arm64/boot/dts/qcom/ipq5424.dtsi | 30 ++++++++++++++++++++++++++++++ >> 1 file changed, 30 insertions(+) >> >> diff --git a/arch/arm64/boot/dts/qcom/ipq5424.dtsi b/arch/arm64/boot/dts/qcom/ipq5424.dtsi >> index 2eea8a078595..eb4aa778269c 100644 >> --- a/arch/arm64/boot/dts/qcom/ipq5424.dtsi >> +++ b/arch/arm64/boot/dts/qcom/ipq5424.dtsi >> @@ -730,6 +730,36 @@ frame@f42d000 { >> }; >> }; >> >> + clock-controller@39b00000 { >> + compatible = "qcom,ipq5424-nsscc"; >> + reg = <0 0x39b00000 0 0x800>; > > size = 0x100_000 > > with that: > > Reviewed-by: Konrad Dybcio > > Konrad I initially thought that a block size of 0x800 would be sufficient, as it covers the maximum address range needed for the clock configurations. However, the NSS clock controller block actually occupies an address range of 0x80000. I will update this to 0x80000 in the next version. Thank you for your feedback.