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[103.229.16.4]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-3ac6006376bsm3136909a91.3.2026.10.14.00.13.50 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 14 Oct 2026 00:13:57 -0700 (PDT) Message-ID: Date: Wed, 14 Oct 2026 15:13:48 +0800 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH DNM v3 8/8] arm64: dts: qcom: kaanapali: Add MPAM MSC nodes for the L2 caches To: Konrad Dybcio , Ben Horgan , Rob Herring Cc: James Morse , Shanker Donthineni , Krzysztof Kozlowski , Conor Dooley , Catalin Marinas , Greg Kroah-Hartman , "Rafael J. Wysocki" , Danilo Krummrich , Reinette Chatre , Fenghua Yu , Jonathan Cameron , Bjorn Andersson , Konrad Dybcio , Gavin Shan , Andre Przywara , Drew Fustini , =?UTF-8?Q?Ilpo_J=C3=A4rvinen?= , Shaopeng Tan , trilok.soni@oss.qualcomm.com, aiqun.yu@oss.qualcomm.com, ganapatrao.kulkarni@oss.qualcomm.com, Srivathsa L Rao , Huang Yiwei , linux-arm-kernel@lists.infradead.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, driver-core@lists.linux.dev, devicetree@vger.kernel.org References: <20261008-mpam-resctrl-dt-knp-support-v3-0-35196c2b43bf@oss.qualcomm.com> <20261008-mpam-resctrl-dt-knp-support-v3-8-35196c2b43bf@oss.qualcomm.com> <20261008210004.GA1318789-robh@kernel.org> <1d764a3d-7935-4e26-b1c2-92537e1d3811@oss.qualcomm.com> <893507ca-b956-474c-9124-92fbfc25e9ab@arm.com> <21f0c2f7-48a5-466b-9dd3-170a04e3af9c@oss.qualcomm.com> Content-Language: en-US From: Yin Li In-Reply-To: <21f0c2f7-48a5-466b-9dd3-170a04e3af9c@oss.qualcomm.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYxMDE0MDAyOCBTYWx0ZWRfX3MaCtETbIRKT 7eDu1CtGYc42+M3YPt+TBPkISXitUmnCMSqxZNYxfuqN5DveV0WOXTfwDpng07ltcu2ncrLNzXl cr/PjZHxzjH710eOlWCht4TpwueBE2chszzpT6a3HGTuV+437/s5eUfcpZsXSahe/j3br0833Ry 3MHPXvyyT939u3ZiO4Nei5fFl8h9xasjcwq6MisZ3+AJA/mIgbaTQSIr4sMj41Lja5p+uLtXakp wKDKJBHF3impK3xLP2doKOZwfK2pRMRsJEY3D/+F+l3pPfBvoC9ZHrWvC/LEEsKPZ1l3evFdvZM HoLFnSz73D1CJ73akyun4eQyethnIoYYXhcFkfCw/WFtZ7kPT3MRTphWwYBcKUnNV/fxT2gvZzP WxJCFshzroeO/JfRR/AxvFciOEGb7zLrh+zJ2Q4/mQw6VQCp/NVQJzxj36zkoyqGSOG/XUGjJ9a Qn+FKHYfHU4y/CSITQQ== X-Authority-Analysis: v=2.4 cv=Jp1kP84C c=1 sm=1 tr=0 ts=6acf2bb7 cx=c_pps a=UNFcQwm+pnOIJct1K4W+Mw==:117 a=nuhDOHQX5FNHPW3J6Bj6AA==:17 a=IkcTkHD0fZMA:10 a=660iZSQnnn4A:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=3WHJM1ZQz_JShphwDgj5:22 a=EUspDBNiAAAA:8 a=0BaB_ceHjnLeFdfrkW8A:9 a=3ZKOabzyN94A:10 a=QEXdDO2ut3YA:10 a=uKXjsCUrEbL0IQVhDsJ9:22 X-Proofpoint-GUID: Vt6LSKzpRs-njMgs5GDWOtgMt1kwHoUl X-Proofpoint-ORIG-GUID: Vt6LSKzpRs-njMgs5GDWOtgMt1kwHoUl X-Proofpoint-Spam-Info: AW1haW4tMjYxMDE0MDAyOCBTYWx0ZWRfX+YcRM82PnWFh hPhhS3+Zhb49ON3g9bvyvipDM0XiiqH2t1TntumGGn6tewIM8GPNCt8pLx9Cj8IN/VF51AU3FWu +eMKePTfz2ctyx7blCWzo9Gf62j/mGs= X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-10-13_01,2026-10-09_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 suspectscore=0 lowpriorityscore=0 clxscore=1015 spamscore=0 priorityscore=1501 bulkscore=0 adultscore=0 impostorscore=0 phishscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2610080000 definitions=main-2610140028 On 10/13/2026 6:54 PM, Konrad Dybcio wrote: > On 10/13/26 12:13 PM, Yin Li wrote: >> >> >> On 10/12/2026 7:27 PM, Ben Horgan wrote: >>> Hi Yin, >>> >>> On 12/10/2026 11:48, Yin Li wrote: >>>> >>>> >>>> On 10/9/2026 5:00 AM, Rob Herring wrote: >>>>> On Thu, Oct 08, 2026 at 02:41:17PM +0800, Yin Li wrote: >>>>>> Add an MPAM MSC device node for each L2 cache. Each MSC is nested >>>>>> directly under its L2 cache node so that the cache node is the MSC's >>>>>> parent device and its CPU affinity is derived from that cache. >>>>>> >>>>>> The L2 cache nodes are placed directly under the root node. The root is >>>>>> the root of the physical address space, so each cache node only needs an >>>>>> identity 'ranges' property for its nested MSC's 'reg' to be resolved to >>>>>> a physical address. The two caches use distinct node names (l2-cache-0 >>>>>> and l2-cache-1) since a cache node has no MMIO unit-address of its own. >>>>>> >>>>>> The nodes are disabled by default. Production firmware does not expose >>>>>> MSC register access to the OS, so these nodes can only be enabled on a >>>>>> local test setup where firmware permits direct MMIO access to the MSCs. >>>>>> This DTS is therefore only an example for other platform DT authors and >>>>>> is not intended to be merged. >>>>>> >>>>>> Co-developed-by: Huang Yiwei >>>>>> Signed-off-by: Huang Yiwei >>>>>> Signed-off-by: Yin Li >>>>>> --- >>>>>>    arch/arm64/boot/dts/qcom/kaanapali.dtsi | 50 +++++++++++++++++++++++++-------- >>>>>>    1 file changed, 38 insertions(+), 12 deletions(-) >>>>>> >>>>>> diff --git a/arch/arm64/boot/dts/qcom/kaanapali.dtsi b/arch/arm64/boot/dts/qcom/kaanapali.dtsi >>>>>> index 131fd2a16c54..b1dcb1e9c570 100644 >>>>>> --- a/arch/arm64/boot/dts/qcom/kaanapali.dtsi >>>>>> +++ b/arch/arm64/boot/dts/qcom/kaanapali.dtsi >>> >>> [...] >>> >>>> >>>>>> + >>>>>> +        msc@19870000 { >>>>>> +            compatible = "arm,mpam-msc"; >>>>>> +            reg = <0x0 0x19870000 0x0 0x10000>; >>>>> >>>>> The MPAM register length is 0x321C. >>>>> >>>> >>>> You are right, the MPAM register space is 0x321c per the specification. >>>> Will update accordingly. > > In Qualcomm DTs we tend to use the ""how much register space is allocated > for this block"" rather than ""what the last used register ends"" approach > to avoid holes > Hi Konrad, Thanks for the context. Thanks, Yin > Konrad -- Thx and BRs, Yin