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[103.229.16.4]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2beca535bc1sm48134085ad.56.2026.05.25.05.13.36 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 25 May 2026 05:13:40 -0700 (PDT) Message-ID: Date: Mon, 25 May 2026 20:13:35 +0800 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v4 16/39] drm/msm/dp: use stream_id to change offsets in dp_catalog To: Dmitry Baryshkov Cc: Rob Clark , Dmitry Baryshkov , Abhinav Kumar , Sean Paul , Marijn Suijten , David Airlie , Simona Vetter , Jessica Zhang , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org, Abhinav Kumar References: <20260410-msm-dp-mst-v4-0-b20518dea8de@oss.qualcomm.com> <20260410-msm-dp-mst-v4-16-b20518dea8de@oss.qualcomm.com> <753dde5f-9032-40ed-832b-0ecba7228d1a@oss.qualcomm.com> Content-Language: en-US From: Yongxing Mou In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNTI1MDEyNiBTYWx0ZWRfXzmOB0nGsWI0+ Zb9erRIWbWaaSk+vNgksJHrUG35ckOoykJpMSo90M0leqYb+R1yM3L7MqIQ9cVmY9LsE4E7Z3SL xcySTyo0m1BrhdtmsptfI8zemn6Wmfr6QywXtjKqzpIESzwUU7HGZBirkeAieLr/w7V/pHS04DA AimbkFoxp7HMWL0ZmKJXtNV2g2HeRywspz4vU2gpdsFaDielhucHJxtVFG6IrRMl9B7aMhH2kXQ EFbQ6e4Wk8fFHDxcm0TsLMCuDNI8o9D/5lt8KtyCtyLzdXZHnx8en0C0IU1Hz7lMCfMlE0gEcmH nyhu8F8GWPA4ZqbAnFE/vj2pRPfLM1Hmd59RqtF/mkhHY1TQObIlA4ddWMhfnNbZhGW15yzvxm8 JnPfsqg2slM7nD4RP2SFYArMy3b6X0H6PfLkO/S60/jTPAo8opKt1cFthskWw+HnQRVd682LMvC n9j7fsPX+dTMugE0+rQ== X-Proofpoint-GUID: F1eYMHdVUWVJWzV3sBoaYLB4wRzdwglK X-Proofpoint-ORIG-GUID: F1eYMHdVUWVJWzV3sBoaYLB4wRzdwglK X-Authority-Analysis: v=2.4 cv=XqTK/1F9 c=1 sm=1 tr=0 ts=6a143cf6 cx=c_pps a=IZJwPbhc+fLeJZngyXXI0A==:117 a=nuhDOHQX5FNHPW3J6Bj6AA==:17 a=IkcTkHD0fZMA:10 a=NGcC8JguVDcA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=YMgV9FUhrdKAYTUUvYB2:22 a=COk6AnOGAAAA:8 a=EUspDBNiAAAA:8 a=6FVArigR0TE__iZ8T84A:9 a=QEXdDO2ut3YA:10 a=uG9DUKGECoFWVXl0Dc02:22 a=TjNXssC_j7lpFel5tvFf:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-05-25_03,2026-05-18_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 phishscore=0 priorityscore=1501 lowpriorityscore=0 suspectscore=0 spamscore=0 adultscore=0 clxscore=1015 bulkscore=0 impostorscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2605130000 definitions=main-2605250126 On 5/25/2026 4:21 PM, Dmitry Baryshkov wrote: > On Mon, May 25, 2026 at 04:06:08PM +0800, Yongxing Mou wrote: >> >> >> On 4/12/2026 2:12 AM, Dmitry Baryshkov wrote: >>> On Fri, Apr 10, 2026 at 05:33:51PM +0800, Yongxing Mou wrote: >>>> From: Abhinav Kumar >>>> >>>> Use the dp_panel's stream_id to adjust the offsets for stream 1 which will >>>> be used for MST in the dp_catalog. >>> >>> Please start by describing the problem. >>> >> Got it, thanks. >>>> Stream 1 share the same link clk with >>>> stream 0 with different reg offset. Also add additional register defines >>>> for stream 1. >>>> >>>> Streams 2 and 3 are not covered here, as they use separate link clocks and >>>> require separate handling. >>>> >>>> Signed-off-by: Abhinav Kumar >>>> Signed-off-by: Yongxing Mou >>>> --- >>>> drivers/gpu/drm/msm/dp/dp_ctrl.c | 24 ++++++++++--- >>>> drivers/gpu/drm/msm/dp/dp_panel.c | 72 +++++++++++++++++++++++++++------------ >>>> drivers/gpu/drm/msm/dp/dp_reg.h | 11 ++++++ >>>> 3 files changed, 81 insertions(+), 26 deletions(-) >>>> >>>> diff --git a/drivers/gpu/drm/msm/dp/dp_reg.h b/drivers/gpu/drm/msm/dp/dp_reg.h >>>> index 3689642b7fc0..295c1161e6b7 100644 >>>> --- a/drivers/gpu/drm/msm/dp/dp_reg.h >>>> +++ b/drivers/gpu/drm/msm/dp/dp_reg.h >>>> @@ -332,6 +332,17 @@ >>>> #define DP_TPG_VIDEO_CONFIG_BPP_8BIT (0x00000001) >>>> #define DP_TPG_VIDEO_CONFIG_RGB (0x00000004) >>>> +/* DP MST registers */ >>> >>> Which register spaces are they from? >>> >> Here also from DPTX_*, what about this? /* DP_TX MST registers */ > > Why? don't separate them from the registers from the same space. Also, > please, name them uniformly. Why some of those are REG_DP1 and others > are MMSS_DP1? > Hmm. So should I just delete this comments and sort them in ascending address order? Regarding REG_DP1_ and MMSS_DP1_, this is a historical naming convention inherited from the existing code. >>>> +#define REG_DP1_CONFIGURATION_CTRL (0x00000400) >>>> +#define REG_DP1_SOFTWARE_MVID (0x00000414) >>>> +#define REG_DP1_SOFTWARE_NVID (0x00000418) >>>> +#define REG_DP1_TOTAL_HOR_VER (0x0000041C) >>>> +#define REG_DP1_MISC1_MISC0 (0x0000042C) >>>> +#define MMSS_DP1_GENERIC0_0 (0x00000490) >>>> +#define MMSS_DP1_SDP_CFG (0x000004E0) >>>> +#define MMSS_DP1_SDP_CFG2 (0x000004E4) >>>> +#define MMSS_DP1_SDP_CFG3 (0x000004E8) >>>> + >>>> #define MMSS_DP_ASYNC_FIFO_CONFIG (0x00000088) >>>> #define REG_DP_PHY_AUX_INTERRUPT_CLEAR (0x0000004C) >>>> >