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Fri, 07 Feb 2025 01:12:24 +0000 (GMT) Received: from nasanex01b.na.qualcomm.com (nasanex01b.na.qualcomm.com [10.46.141.250]) by NASANPPMTA02.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 5171CNSN021634 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 7 Feb 2025 01:12:23 GMT Received: from [10.134.70.212] (10.80.80.8) by nasanex01b.na.qualcomm.com (10.46.141.250) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Thu, 6 Feb 2025 17:12:23 -0800 Message-ID: Date: Thu, 6 Feb 2025 17:12:22 -0800 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v5 02/15] drm/msm/dpu: Do not fix number of DSC Content-Language: en-US To: Jun Nie , Rob Clark , "Abhinav Kumar" , Dmitry Baryshkov , Sean Paul , Marijn Suijten , David Airlie , "Simona Vetter" CC: , , , References: <20250118-sm8650-v6-13-hmd-deckard-mdss-quad-upstream-33-v5-0-9701a16340da@linaro.org> <20250118-sm8650-v6-13-hmd-deckard-mdss-quad-upstream-33-v5-2-9701a16340da@linaro.org> From: Jessica Zhang In-Reply-To: <20250118-sm8650-v6-13-hmd-deckard-mdss-quad-upstream-33-v5-2-9701a16340da@linaro.org> Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 7bit X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nasanex01b.na.qualcomm.com (10.46.141.250) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: XUMyrgYLEGu86sMivONuV1FqxgQYhqPM X-Proofpoint-GUID: XUMyrgYLEGu86sMivONuV1FqxgQYhqPM X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1057,Hydra:6.0.680,FMLib:17.12.68.34 definitions=2025-02-07_01,2025-02-05_03,2024-11-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0 malwarescore=0 lowpriorityscore=0 impostorscore=0 adultscore=0 clxscore=1015 mlxscore=0 mlxlogscore=999 spamscore=0 bulkscore=0 phishscore=0 priorityscore=1501 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2501170000 definitions=main-2502070007 On 1/17/2025 8:00 AM, Jun Nie wrote: > Currently, if DSC is enabled, only 2 DSC engines are supported so far. > More usage cases will be added, such as 4 DSC in 4:4:2 topology. So > get the real number of DSCs to decide whether DSC merging is needed. > > Signed-off-by: Jun Nie > Reviewed-by: Dmitry Baryshkov Reviewed-by: Jessica Zhang > --- > drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 6 ++++-- > 1 file changed, 4 insertions(+), 2 deletions(-) > > diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c > index eaac172141ede..c734d2c5790d2 100644 > --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c > +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c > @@ -164,6 +164,7 @@ enum dpu_enc_rc_states { > * clks and resources after IDLE_TIMEOUT time. > * @topology: topology of the display > * @idle_timeout: idle timeout duration in milliseconds > + * @num_dscs: Number of DSCs in use > * @wide_bus_en: wide bus is enabled on this interface > * @dsc: drm_dsc_config pointer, for DSC-enabled encoders > */ > @@ -204,6 +205,7 @@ struct dpu_encoder_virt { > struct msm_display_topology topology; > > u32 idle_timeout; > + u32 num_dscs; > > bool wide_bus_en; > > @@ -622,9 +624,8 @@ bool dpu_encoder_use_dsc_merge(struct drm_encoder *drm_enc) > if (dpu_enc->phys_encs[i]) > intf_count++; > > - /* See dpu_encoder_get_topology, we only support 2:2:1 topology */ > if (dpu_enc->dsc) > - num_dsc = 2; > + num_dsc = dpu_enc->num_dscs; > > return (num_dsc > 0) && (num_dsc > intf_count); > } > @@ -1261,6 +1262,7 @@ static void dpu_encoder_virt_atomic_mode_set(struct drm_encoder *drm_enc, > dsc_mask |= BIT(dpu_enc->hw_dsc[i]->idx - DSC_0); > } > > + dpu_enc->num_dscs = num_dsc; > dpu_enc->dsc_mask = dsc_mask; > > if ((dpu_enc->disp_info.intf_type == INTF_WB && conn_state->writeback_job) || > > -- > 2.34.1 >