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Wed, 03 Apr 2024 05:30:20 +0000 (GMT) Received: from nalasex01c.na.qualcomm.com (nalasex01c.na.qualcomm.com [10.47.97.35]) by NALASPPMTA05.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 4335UJZQ031508 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 3 Apr 2024 05:30:19 GMT Received: from [10.239.154.73] (10.80.80.8) by nalasex01c.na.qualcomm.com (10.47.97.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.4; Tue, 2 Apr 2024 22:30:13 -0700 Message-ID: Date: Wed, 3 Apr 2024 13:29:46 +0800 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v8 1/3] input: pm8xxx-vibrator: refactor to support new SPMI vibrator Content-Language: en-US To: Konrad Dybcio , , Andy Gross , Bjorn Andersson , Dmitry Torokhov , Rob Herring , "Krzysztof Kozlowski" , Dmitry Baryshkov CC: , , , References: <20240401-pm8xxx-vibrator-new-design-v8-0-6f2b8b03b4c7@quicinc.com> <20240401-pm8xxx-vibrator-new-design-v8-1-6f2b8b03b4c7@quicinc.com> <21641459-d7c0-412d-8244-6f2f2c458551@linaro.org> From: Fenglin Wu In-Reply-To: <21641459-d7c0-412d-8244-6f2f2c458551@linaro.org> Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 7bit X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01c.na.qualcomm.com (10.47.97.35) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: ptSWHyJ8d6MRM52jQtVZhkIlouK4omGN X-Proofpoint-GUID: ptSWHyJ8d6MRM52jQtVZhkIlouK4omGN X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.1011,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2024-04-03_04,2024-04-01_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 phishscore=0 priorityscore=1501 suspectscore=0 mlxscore=0 bulkscore=0 malwarescore=0 mlxlogscore=607 clxscore=1011 spamscore=0 impostorscore=0 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2403210001 definitions=main-2404030035 On 4/2/2024 11:21 PM, Konrad Dybcio wrote: > On 1.04.2024 10:38 AM, Fenglin Wu via B4 Relay wrote: >> From: Fenglin Wu >> >> Currently, vibrator control register addresses are hard coded, >> including the base address and offsets, it's not flexible to >> support new SPMI vibrator module which is usually included in >> different PMICs with different base address. Refactor it by using >> the base address defined in devicetree. >> >> Signed-off-by: Fenglin Wu >> --- > > [...] > >> if (regs->enable_mask) >> - rc = regmap_update_bits(vib->regmap, regs->enable_addr, >> + rc = regmap_update_bits(vib->regmap, vib->enable_addr, >> regs->enable_mask, on ? ~0 : 0); > > The idiomatic way across the kernel seems to be writing the mask value > instead of ~0 (which also saves like 2 cpu instructions) > > > Not sure about how ssbi addressing works, but except for that lgtm > Agree. SSBI driver doesn't provide reg_update_bits function call so similar mathematics is done on the value before writing to the register, I can update it to use enable_mask directly in next version. > Konrad