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Fri, 3 Oct 2025 08:35:46 +0000 (UTC) Received: from dovecot-director2.suse.de ([2a07:de40:b281:106:10:150:64:167]) by imap1.dmz-prg2.suse.org with ESMTPSA id xeiGHOKK32gNcgAAD6G6ig (envelope-from ); Fri, 03 Oct 2025 08:35:46 +0000 Message-ID: Date: Fri, 3 Oct 2025 10:35:46 +0200 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2 2/4] mm/page_alloc: Perform appropriate batching in drain_pages_zone Content-Language: en-US To: Hillf Danton , Joshua Hahn Cc: Andrew Morton , Johannes Weiner , linux-kernel@vger.kernel.org, linux-mm@kvack.org, kernel-team@meta.com, Chris Mason , Kiryl Shutsemau , "Liam R. Howlett" , Brendan Jackman , David Hildenbrand , Lorenzo Stoakes , Michal Hocko , Mike Rapoport , Suren Baghdasaryan , Vlastimil Babka , Zi Yan , Hillf Danton , linux-kernel@vger.kernel.org, linux-mm@kvack.org, kernel-team@meta.com References: <20251001234814.7896-1-hdanton@sina.com> From: Vlastimil Babka In-Reply-To: <20251001234814.7896-1-hdanton@sina.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Spamd-Result: default: False [-2.80 / 50.00]; BAYES_HAM(-3.00)[99.99%]; SUSPICIOUS_RECIPS(1.50)[]; NEURAL_HAM_LONG(-1.00)[-1.000]; NEURAL_HAM_SHORT(-0.20)[-1.000]; MIME_GOOD(-0.10)[text/plain]; FREEMAIL_ENVRCPT(0.00)[gmail.com,sina.com]; RCVD_TLS_ALL(0.00)[]; ARC_NA(0.00)[]; RCVD_VIA_SMTP_AUTH(0.00)[]; MIME_TRACE(0.00)[0:+]; FUZZY_RATELIMITED(0.00)[rspamd.com]; RCPT_COUNT_TWELVE(0.00)[22]; TAGGED_RCPT(0.00)[]; MID_RHS_MATCH_FROM(0.00)[]; TO_DN_SOME(0.00)[]; FROM_HAS_DN(0.00)[]; FREEMAIL_CC(0.00)[linux-foundation.org,cmpxchg.org,vger.kernel.org,kvack.org,meta.com,fb.com,shutemov.name,oracle.com,google.com,redhat.com,suse.com,kernel.org,suse.cz,nvidia.com,sina.com]; FREEMAIL_TO(0.00)[sina.com,gmail.com]; FROM_EQ_ENVFROM(0.00)[]; RCVD_COUNT_TWO(0.00)[2]; TO_MATCH_ENVRCPT_ALL(0.00)[]; DKIM_SIGNED(0.00)[suse.cz:s=susede2_rsa,suse.cz:s=susede2_ed25519]; DBL_BLOCKED_OPENRESOLVER(0.00)[imap1.dmz-prg2.suse.org:helo] X-Spam-Flag: NO X-Spam-Level: X-Spam-Score: -2.80 On 10/2/25 01:48, Hillf Danton wrote: > On Wed, 1 Oct 2025 08:37:16 -0700 Joshua Hahn wrote: >> >> While I definitely agree that spreading out 1TB across multiple NUMA nodes >> is an option that should be considered, I am unsure if it makes sense to >> dismiss this issue as simply a misconfiguration problem. >> >> The reality is that these machines do exist, and we see zone lock contention >> on these machines. You can also see that I ran performance evaluation tests >> on relatively smaller machines (250G) and saw some performance gains. >> > If NUMA node could not be an option, there is still much room in the zone types > for adding new zones on top of the current pcp and zone mechanism to mitigate > zone lock contention, see diff below. Then the issue falls in the config category. > >> The other point that I wanted to mention is that simply adding more NUMA >> nodes is not always strictly beneficial; it changes how the scheduler >> has to work, workloads would require more numa-aware tuning, etc. > > Feel safe to sit back with Netflix on as PeterZ is taking care of NUMA nodes > and eevdf, haha. Feel free to stop making such weird "jokes"? Also you should really stop dropping CC's on your replies, especially for maintainers of given code. I've only learned in the v3 changelog from "as suggested by Hillf Danton" that there was this subthread. This is not acceptable. When the feedback is wrong and uncorrected by others, it can mislead the patch author to do wrong changes in the next version. If this Cc reduction is due to a problem with your e-mail provider, get a different one? > --- x/include/linux/mmzone.h > +++ y/include/linux/mmzone.h > @@ -779,6 +779,9 @@ enum zone_type { > #ifdef CONFIG_ZONE_DMA32 > ZONE_DMA32, > #endif > +#ifdef CONFIG_ZONE_EXP > + ZONE_EXP0, ZONE_EXP1, ZONE_EXP2, /* experiment */ > +#endif > /* > * Normal addressable memory is in ZONE_NORMAL. DMA operations can be > * performed on pages in ZONE_NORMAL if the DMA devices support >