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X-OriginatorOrg: foss.st.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 12 Sep 2025 14:55:43.8627 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: a29b0df2-28e9-44c2-9161-08ddf20c7302 X-MS-Exchange-CrossTenant-Id: 75e027c9-20d5-47d5-b82f-77d7cd041e8f X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=75e027c9-20d5-47d5-b82f-77d7cd041e8f;Ip=[164.130.1.43];Helo=[smtpO365.st.com] X-MS-Exchange-CrossTenant-AuthSource: AM2PEPF0001C711.eurprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PAWPR10MB8259 X-Authority-Analysis: v=2.4 cv=OaqYDgTY c=1 sm=1 tr=0 ts=68c43472 cx=c_pps a=TPI4aLKDjCd1EbHbt8/hbw==:117 a=peP7VJn1Wk7OJvVWh4ABVQ==:17 a=6eWqkTHjU83fiwn7nKZWdM+Sl24=:19 a=h8e1o3o8w34MuCiiGQrqVE4VwXA=:19 a=wKuvFiaSGQ0qltdbU6+NXLB8nM8=:19 a=Ol13hO9ccFRV9qXi2t6ftBPywas=:19 a=d2j-ISUXm-8A:10 a=IkcTkHD0fZMA:10 a=yJojWOMRYYMA:10 a=s63m1ICgrNkA:10 a=KrXZwBdWH7kA:10 a=pGLkceISAAAA:8 a=8b9GpE9nAAAA:8 a=RuKwHrkmIdvFytnfrUcA:9 a=QEXdDO2ut3YA:10 a=T3LWEMljR5ZiDmsYVIUa:22 X-Proofpoint-ORIG-GUID: S784noySfHsOQOEe0kyVyaW-L8ObPYi- X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwOTA3MDAwNiBTYWx0ZWRfXxFoQn9IkcGw0 rJv4fJ+fpE54W9xcLyvrpHUQ488WeyLwbX/EeIXRqA5uQA8W7J6C6A4x20p6YAHe8NE7653kli1 V0HQUkV/3EXcQSXIKF6ib6pJoN6AvQXTlVjw5otBaicohz4igHR7hPkJqLbetk7ablp4IceeFT7 gwO6/+7gary47h4257RrOA9ywwhL9xkr/JGiZMt9jk8rzljYFKO0njKbmBs1qYIiK5aT0uMNNOB 7h8iUAynBVvYe7xvFRDpNuLtZzE/kOW9Ph2PQlbUq+eCnmBns/HQJaUiLCGaQHbjgpccs3L+RpZ x6v1TKmm/0NRG8/TbWNN+SN5EvuwYsBWD3RoSE4+U/FxcmzE/q44VKKf2V4nTRsrP3e8FiWohVh h5l7CBEu X-Proofpoint-GUID: S784noySfHsOQOEe0kyVyaW-L8ObPYi- X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1117,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-09-12_05,2025-09-11_02,2025-03-28_01 X-Proofpoint-Spam-Details: rule=notspam policy=default score=0 phishscore=0 clxscore=1015 suspectscore=0 bulkscore=0 adultscore=0 priorityscore=1501 malwarescore=0 spamscore=0 impostorscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2507300000 definitions=main-2509070006 On 9/12/25 16:43, Patrice CHOTARD wrote: > > > On 9/8/25 09:21, Raphael Gallais-Pou wrote: >> Following the removal of B2120 board support, the st/stih407-clock.dtsi >> file has been left unused. Remove it. >> >> Fixes: dee546e1adef ("ARM: sti: drop B2120 board support") >> Signed-off-by: Raphael Gallais-Pou >> --- >> arch/arm/boot/dts/st/stih407-clock.dtsi | 210 -------------------------------- >> 1 file changed, 210 deletions(-) >> >> diff --git a/arch/arm/boot/dts/st/stih407-clock.dtsi b/arch/arm/boot/dts/st/stih407-clock.dtsi >> deleted file mode 100644 >> index 350bcfcf498bc410ebdb4fd00f2e1ea496a9c8be..0000000000000000000000000000000000000000 >> --- a/arch/arm/boot/dts/st/stih407-clock.dtsi >> +++ /dev/null >> @@ -1,210 +0,0 @@ >> -// SPDX-License-Identifier: GPL-2.0-only >> -/* >> - * Copyright (C) 2014 STMicroelectronics R&D Limited >> - */ >> -#include >> -/ { >> - /* >> - * Fixed 30MHz oscillator inputs to SoC >> - */ >> - clk_sysin: clk-sysin { >> - #clock-cells = <0>; >> - compatible = "fixed-clock"; >> - clock-frequency = <30000000>; >> - }; >> - >> - clk_tmdsout_hdmi: clk-tmdsout-hdmi { >> - #clock-cells = <0>; >> - compatible = "fixed-clock"; >> - clock-frequency = <0>; >> - }; >> - >> - clocks { >> - #address-cells = <1>; >> - #size-cells = <1>; >> - ranges; >> - >> - /* >> - * A9 PLL. >> - */ >> - clockgen-a9@92b0000 { >> - compatible = "st,clkgen-c32"; >> - reg = <0x92b0000 0x10000>; >> - >> - clockgen_a9_pll: clockgen-a9-pll { >> - #clock-cells = <1>; >> - compatible = "st,stih407-clkgen-plla9"; >> - >> - clocks = <&clk_sysin>; >> - }; >> - >> - clk_m_a9: clk-m-a9 { >> - #clock-cells = <0>; >> - compatible = "st,stih407-clkgen-a9-mux"; >> - >> - clocks = <&clockgen_a9_pll 0>, >> - <&clockgen_a9_pll 0>, >> - <&clk_s_c0_flexgen 13>, >> - <&clk_m_a9_ext2f_div2>; >> - >> - /* >> - * ARM Peripheral clock for timers >> - */ >> - arm_periph_clk: clk-m-a9-periphs { >> - #clock-cells = <0>; >> - compatible = "fixed-factor-clock"; >> - >> - clocks = <&clk_m_a9>; >> - clock-div = <2>; >> - clock-mult = <1>; >> - }; >> - }; >> - }; >> - >> - clockgen-a@90ff000 { >> - compatible = "st,clkgen-c32"; >> - reg = <0x90ff000 0x1000>; >> - >> - clk_s_a0_pll: clk-s-a0-pll { >> - #clock-cells = <1>; >> - compatible = "st,clkgen-pll0-a0"; >> - >> - clocks = <&clk_sysin>; >> - }; >> - >> - clk_s_a0_flexgen: clk-s-a0-flexgen { >> - compatible = "st,flexgen", "st,flexgen-stih407-a0"; >> - >> - #clock-cells = <1>; >> - >> - clocks = <&clk_s_a0_pll 0>, >> - <&clk_sysin>; >> - }; >> - }; >> - >> - clk_s_c0: clockgen-c@9103000 { >> - compatible = "st,clkgen-c32"; >> - reg = <0x9103000 0x1000>; >> - >> - clk_s_c0_pll0: clk-s-c0-pll0 { >> - #clock-cells = <1>; >> - compatible = "st,clkgen-pll0-c0"; >> - >> - clocks = <&clk_sysin>; >> - }; >> - >> - clk_s_c0_pll1: clk-s-c0-pll1 { >> - #clock-cells = <1>; >> - compatible = "st,clkgen-pll1-c0"; >> - >> - clocks = <&clk_sysin>; >> - }; >> - >> - clk_s_c0_quadfs: clk-s-c0-quadfs { >> - #clock-cells = <1>; >> - compatible = "st,quadfs-pll"; >> - >> - clocks = <&clk_sysin>; >> - }; >> - >> - clk_s_c0_flexgen: clk-s-c0-flexgen { >> - #clock-cells = <1>; >> - compatible = "st,flexgen", "st,flexgen-stih407-c0"; >> - >> - clocks = <&clk_s_c0_pll0 0>, >> - <&clk_s_c0_pll1 0>, >> - <&clk_s_c0_quadfs 0>, >> - <&clk_s_c0_quadfs 1>, >> - <&clk_s_c0_quadfs 2>, >> - <&clk_s_c0_quadfs 3>, >> - <&clk_sysin>; >> - >> - /* >> - * ARM Peripheral clock for timers >> - */ >> - clk_m_a9_ext2f_div2: clk-m-a9-ext2f-div2s { >> - #clock-cells = <0>; >> - compatible = "fixed-factor-clock"; >> - >> - clocks = <&clk_s_c0_flexgen 13>; >> - >> - clock-output-names = "clk-m-a9-ext2f-div2"; >> - >> - clock-div = <2>; >> - clock-mult = <1>; >> - }; >> - }; >> - }; >> - >> - clockgen-d0@9104000 { >> - compatible = "st,clkgen-c32"; >> - reg = <0x9104000 0x1000>; >> - >> - clk_s_d0_quadfs: clk-s-d0-quadfs { >> - #clock-cells = <1>; >> - compatible = "st,quadfs-d0"; >> - >> - clocks = <&clk_sysin>; >> - }; >> - >> - clk_s_d0_flexgen: clk-s-d0-flexgen { >> - #clock-cells = <1>; >> - compatible = "st,flexgen", "st,flexgen-stih407-d0"; >> - >> - clocks = <&clk_s_d0_quadfs 0>, >> - <&clk_s_d0_quadfs 1>, >> - <&clk_s_d0_quadfs 2>, >> - <&clk_s_d0_quadfs 3>, >> - <&clk_sysin>; >> - }; >> - }; >> - >> - clockgen-d2@9106000 { >> - compatible = "st,clkgen-c32"; >> - reg = <0x9106000 0x1000>; >> - >> - clk_s_d2_quadfs: clk-s-d2-quadfs { >> - #clock-cells = <1>; >> - compatible = "st,quadfs-d2"; >> - >> - clocks = <&clk_sysin>; >> - }; >> - >> - clk_s_d2_flexgen: clk-s-d2-flexgen { >> - #clock-cells = <1>; >> - compatible = "st,flexgen", "st,flexgen-stih407-d2"; >> - >> - clocks = <&clk_s_d2_quadfs 0>, >> - <&clk_s_d2_quadfs 1>, >> - <&clk_s_d2_quadfs 2>, >> - <&clk_s_d2_quadfs 3>, >> - <&clk_sysin>, >> - <&clk_sysin>, >> - <&clk_tmdsout_hdmi>; >> - }; >> - }; >> - >> - clockgen-d3@9107000 { >> - compatible = "st,clkgen-c32"; >> - reg = <0x9107000 0x1000>; >> - >> - clk_s_d3_quadfs: clk-s-d3-quadfs { >> - #clock-cells = <1>; >> - compatible = "st,quadfs-d3"; >> - >> - clocks = <&clk_sysin>; >> - }; >> - >> - clk_s_d3_flexgen: clk-s-d3-flexgen { >> - #clock-cells = <1>; >> - compatible = "st,flexgen", "st,flexgen-stih407-d3"; >> - >> - clocks = <&clk_s_d3_quadfs 0>, >> - <&clk_s_d3_quadfs 1>, >> - <&clk_s_d3_quadfs 2>, >> - <&clk_s_d3_quadfs 3>, >> - <&clk_sysin>; >> - }; >> - }; >> - }; >> -}; >> >> --- >> base-commit: be5d4872e528796df9d7425f2bd9b3893eb3a42c >> change-id: 20250907-master-bb115f5b67ad >> >> Best regards, > > Reviewed-by: Patrice Chotard > > Thanks > Patrice Applied to sti-next Thanks Patrice