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Wed, 16 Nov 2022 06:56:53 GMT Received: from [10.79.43.101] (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.29; Tue, 15 Nov 2022 22:56:49 -0800 Message-ID: Date: Wed, 16 Nov 2022 12:26:46 +0530 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.2.2 Subject: Re: [PATCH v2 05/10] dt-bindings: interconnect: Add sm8350, sc8280xp and generic OSM L3 compatibles Content-Language: en-US To: Bjorn Andersson CC: Bjorn Andersson , Krzysztof Kozlowski , Georgi Djakov , "Rob Herring" , Konrad Dybcio , Mike Tipton , Johan Hovold , , , , References: <20221111032515.3460-1-quic_bjorande@quicinc.com> <20221111032515.3460-6-quic_bjorande@quicinc.com> <20221111180849.hegnho4qeaewuzwz@builder.lan> From: Sibi Sankar In-Reply-To: <20221111180849.hegnho4qeaewuzwz@builder.lan> Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 7bit X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: waBy_m000gAz_6s7v3zetVNm6uIWivZF X-Proofpoint-GUID: waBy_m000gAz_6s7v3zetVNm6uIWivZF X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.219,Aquarius:18.0.895,Hydra:6.0.545,FMLib:17.11.122.1 definitions=2022-11-15_08,2022-11-15_03,2022-06-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxlogscore=999 impostorscore=0 mlxscore=0 spamscore=0 suspectscore=0 malwarescore=0 priorityscore=1501 adultscore=0 phishscore=0 clxscore=1015 bulkscore=0 lowpriorityscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2210170000 definitions=main-2211160049 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 11/11/22 23:38, Bjorn Andersson wrote: > On Fri, Nov 11, 2022 at 04:02:42PM +0530, Sibi Sankar wrote: >> >> >> On 11/11/22 08:55, Bjorn Andersson wrote: >>> Add EPSS L3 compatibles for sm8350 and sc8280xp, but while at it also >>> introduce generic compatible for both qcom,osm-l3 and qcom,epss-l3. >>> >>> Signed-off-by: Bjorn Andersson >>> Tested-by: Steev Klimaszewski >>> --- >>> >>> Changes since v1: >>> - Fixed oneOf to be valid schema >>> - Fixed example to follow schema >>> >>> .../bindings/interconnect/qcom,osm-l3.yaml | 24 ++++++++++++------- >>> 1 file changed, 16 insertions(+), 8 deletions(-) >>> >>> diff --git a/Documentation/devicetree/bindings/interconnect/qcom,osm-l3.yaml b/Documentation/devicetree/bindings/interconnect/qcom,osm-l3.yaml >>> index bf538c0c5a81..aadae4424ba9 100644 >>> --- a/Documentation/devicetree/bindings/interconnect/qcom,osm-l3.yaml >>> +++ b/Documentation/devicetree/bindings/interconnect/qcom,osm-l3.yaml >>> @@ -16,13 +16,21 @@ description: >>> properties: >>> compatible: >>> - enum: >>> - - qcom,sc7180-osm-l3 >>> - - qcom,sc7280-epss-l3 >>> - - qcom,sc8180x-osm-l3 >>> - - qcom,sdm845-osm-l3 >>> - - qcom,sm8150-osm-l3 >>> - - qcom,sm8250-epss-l3 >>> + oneOf: >>> + - items: >>> + - enum: >>> + - qcom,sc7180-osm-l3 >>> + - qcom,sc8180x-osm-l3 >>> + - qcom,sdm845-osm-l3 >>> + - qcom,sm8150-osm-l3 >>> + - const: qcom,osm-l3 >>> + - items: >>> + - enum: >>> + - qcom,sc7280-epss-l3 >>> + - qcom,sc8280xp-epss-l3 >>> + - qcom,sm8250-epss-l3 >>> + - qcom,sm8350-epss-l3 >>> + - const: qcom,epss-l3 >> >> isn't it incorrect to describe qcom,epss-l3 as a working >> backup compatible for sc7280-epss-l3 and sm8250-epss-l3? >> Shouldn't we just add another items list with those 2 as >> enums? >> > > I was about to agree, but the difference between the two sets are which > registers we use to request the speed. > > And per our recent discussion, I was under the impression that this > would be a property of BIT(0) in 0xb0 being set, not which platform > we're running on. > > If that's the case then they are indeed compatible and we should adjust > .ref_perf_state based on per-core DCVS being set or not. > > > So I do think this description is appropriate... Reviewed-by: Sibi Sankar > > Regards, > Bjorn > >>> reg: >>> maxItems: 1 >>> @@ -56,7 +64,7 @@ examples: >>> #define RPMH_CXO_CLK 0 >>> osm_l3: interconnect@17d41000 { >>> - compatible = "qcom,sdm845-osm-l3"; >>> + compatible = "qcom,sdm845-osm-l3", "qcom,osm-l3"; >>> reg = <0x17d41000 0x1400>; >>> clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;