From: "Tanwar, Rahul" <rahul.tanwar@linux.intel.com>
To: Andy Shevchenko <andriy.shevchenko@intel.com>
Cc: mturquette@baylibre.com, sboyd@kernel.org, robh+dt@kernel.org,
robhkernel.org@smile.fi.intel.com, mark.rutland@arm.com,
linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org,
qi-ming.wu@intel.com, yixin.zhu@linux.intel.com,
cheol.yong.kim@intel.com, rahul.tanwar@intel.com
Subject: Re: [PATCH v1 1/2] clk: intel: Add CGU clock driver for a new SoC
Date: Fri, 6 Dec 2019 12:39:51 +0800 [thread overview]
Message-ID: <db9b8978-b9ae-d1bf-2477-78a99b82367a@linux.intel.com> (raw)
In-Reply-To: <20190902122454.GF2680@smile.fi.intel.com>
Hi Andy,
On 2/9/2019 8:24 PM, Andy Shevchenko wrote:
> On Mon, Sep 02, 2019 at 03:20:30PM +0300, Andy Shevchenko wrote:
>> On Mon, Sep 02, 2019 at 03:43:13PM +0800, Tanwar, Rahul wrote:
>>> On 28/8/2019 11:09 PM, Andy Shevchenko wrote:
>>>> On Wed, Aug 28, 2019 at 03:00:17PM +0800, Rahul Tanwar wrote:
>>>> Does val == 0 follows the table, i.e. makes div == 1?
>>> 0 val means output clock is ref clock i.e. div ==1. Agree that adding
>>> .val = 0, .div =1 entry will make it more clear & complete.
>>>
>>>>> + { .val = 0, .div = 1 },
>>>>> + { .val = 1, .div = 2 },
>>>>> + { .val = 2, .div = 3 },
>> 1
>>
>>>>> + { .val = 3, .div = 4 },
>>>>> + { .val = 4, .div = 5 },
>>>>> + { .val = 5, .div = 6 },
>> 1
>>
>>>>> + { .val = 6, .div = 8 },
>>>>> + { .val = 7, .div = 10 },
>>>>> + { .val = 8, .div = 12 },
>> 2
>>
>>>>> + { .val = 9, .div = 16 },
>>>>> + { .val = 10, .div = 20 },
>>>>> + { .val = 11, .div = 24 },
>> 4
>>
>>>>> + { .val = 12, .div = 32 },
>>>>> + { .val = 13, .div = 40 },
>>>>> + { .val = 14, .div = 48 },
>> 8
>>
>>>>> + { .val = 15, .div = 64 },
>> 16
>>
>>
>> So, now we see the pattern:
>>
>> div = val < 3 ? (val + 1) : (1 << ((val - 3) / 3));
> It's not complete, but I think you got the idea.
>
>> So, can we eliminate table?
In the desperation to eliminate table, below is what i can come up with:
struct clk_div_table div_table[16];
int i, j;
for (i = 0; i < 16; i++)
div_table[i].val = i;
for (i = 0, j=0; i < 16; i+=3, j++) {
div_table[i].div = (i == 0) ? (1 << j) : (1 << (j + 1));
if (i == 15)
break;
div_table[i + 1].div = (i == 0) ? ((1 << j) + 1) :
(1 << (j + 1)) + (1 << (j - 1));
div_table[i + 2].div = (3 << j);
}
To me, table still looks a better approach. Also, table is more extendable &
consistent w.r.t. clk framework & other referenced clk drivers.
Whats your opinion ?
Regards,
Rahul
next prev parent reply other threads:[~2019-12-06 4:39 UTC|newest]
Thread overview: 19+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-08-28 7:00 [PATCH v1 0/2] clk: intel: Add a new driver for a new clock controller IP Rahul Tanwar
2019-08-28 7:00 ` [PATCH v1 1/2] clk: intel: Add CGU clock driver for a new SoC Rahul Tanwar
2019-08-28 15:09 ` Andy Shevchenko
2019-09-02 7:43 ` Tanwar, Rahul
2019-09-02 12:20 ` Andy Shevchenko
2019-09-02 12:24 ` Andy Shevchenko
2019-12-06 4:39 ` Tanwar, Rahul [this message]
2019-12-07 14:57 ` Andy Shevchenko
2019-12-24 3:04 ` Stephen Boyd
2019-09-02 22:20 ` Martin Blumenstingl
2019-09-03 9:54 ` Tanwar, Rahul
2019-09-03 18:53 ` Martin Blumenstingl
2019-09-04 8:03 ` Tanwar, Rahul
2019-09-05 20:47 ` Martin Blumenstingl
2019-09-09 14:16 ` Kim, Cheol Yong
2019-09-16 18:36 ` Stephen Boyd
2019-09-03 23:54 ` Stephen Boyd
2019-08-28 7:00 ` [PATCH v1 2/2] dt-bindings: clk: intel: Add bindings document & header file for CGU Rahul Tanwar
2019-12-19 16:33 ` Rob Herring
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